The
Western Design Center
The Western Design Center (WDC), located in Mesa, Arizona, is a company that develops intellectual property for, and licenses manufacture of, MOS Technology 65xx based microprocessors and microcontrollers. WDC was founded in 1978 by a former ...
(WDC) 65C02
microprocessor
A microprocessor is a computer processor (computing), processor for which the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs. The microprocessor contains the arithmetic, logic, a ...
is an enhanced
CMOS
Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss
", , ) is a type of MOSFET, metal–oxide–semiconductor field-effect transistor (MOSFET) semiconductor device fabrication, fabrication process that uses complementary an ...
version of the popular
nMOS-based
8-bit
In computer architecture, 8-bit integers or other data units are those that are 8 bits wide (1 octet). Also, 8-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers or data bu ...
MOS Technology 6502
The MOS Technology 6502 (typically pronounced "sixty-five-oh-two" or "six-five-oh-two") William Mensch and the moderator both pronounce the 6502 microprocessor as ''"sixty-five-oh-two"''. is an 8-bit computing, 8-bit microprocessor that was desi ...
. It uses less power than the original 6502, fixes several problems, and adds new instructions and addressing modes. The power usage is on the order of 10 to 20 times less than the original 6502 running at the same speed; its reduced power consumption has made it useful in
portable computer
A portable computer is a computer designed to be easily moved from one place to another, as opposed to those designed to remain stationary at a single location such as desktops and workstations. These computers usually include a display a ...
roles and industrial
microcontroller
A microcontroller (MC, uC, or μC) or microcontroller unit (MCU) is a small computer on a single integrated circuit. A microcontroller contains one or more CPUs (processor cores) along with memory and programmable input/output peripherals. Pro ...
systems. The 65C02 has also been used in some
home computer
Home computers were a class of microcomputers that entered the market in 1977 and became common during the 1980s. They were marketed to consumers as affordable and accessible computers that, for the first time, were intended for the use of a s ...
s, as well as in
embedded applications, including implanted medical devices.
Development of the WDC 65C02 began in 1981 with samples released in early 1983. The 65C02
was officially released sometime shortly after. WDC licensed the design to
Synertek
Synertek, Inc. was an American semiconductor manufacturer founded in 1973. The initial staff consisted of Bob Schreiner (the CEO), Dan Floyd, Jack Balletto, and Gunnar Wetlesen and Zvi Grinfas. Schreiner, Floyd, Balletto and Wetlesen were all forme ...
,
NCR,
GTE Microcircuits
Automatic Electric Company (A.E. Co.) was an American telephone equipment supplier primarily for independent telephone companies in North America, but also had a worldwide presence. With its line of automatic telephone exchanges, it was also a lo ...
, and
Rockwell Semiconductor Rockwell may refer to:
Arts and entertainment
* ''Rockwell'' (album), a 2009 mini-album by Anni Rossi
* Rockwell, a fictional town and setting of '' They Hunger''
* ''Rockwell'', a 1994 film about Porter Rockwell
* Rockwell, Maine, a fictiona ...
. Rockwell's primary interest was in the embedded market and asked for several new commands to be added to aid in this role. These were later copied back into the baseline version, at which point WDC added two new commands of their own to create the W65C02.
Sanyo
is a former Japanese electronics manufacturer founded in 1947 by Toshio Iue, the brother-in-law of Kōnosuke Matsushita, the founder of Matsushita Electric Industrial, now known as Panasonic. Iue left Matsushita Electric to start his own bu ...
later licensed the design as well, and
Seiko Epson
Seiko Epson Corporation, commonly known as Epson, is a Japanese multinational electronics company and one of the world's largest manufacturers of printers and information- and imaging-related equipment. Headquartered in Suwa, Nagano, Japan, t ...
produced a further modified version as the
HuC6280
The HuC6280 8-bit microprocessor is Japanese company Hudson Soft's improved version of the WDC 65C02 CPU, an upgraded CMOS version of the popular NMOS-based MOS Technology 6502 8-bit CPU, manufactured for Hudson by Seiko Epson and NEC. The most ...
.
Early versions used 40-pin DIP packaging, and were available in 1, 2 and 4 MHz versions, matching the speeds of the original nMOS versions. Later versions were produced in
PLCC and
QFP
A quad flat package (QFP) is a surface-mounted integrated circuit package with "gull wing" leads extending from each of the four sides. Socketing such packages is rare and through-hole mounting is not possible. Versions ranging from 32 to 304 ...
packages, as well as PDIP, and with much higher clock speed ratings. The current version from WDC, the W65C02S-14 has a fully static core and officially runs at speeds up to 14 MHz when powered at 5 volts.
Introduction and features
The 65C02 is a low cost, general-purpose
8-bit
In computer architecture, 8-bit integers or other data units are those that are 8 bits wide (1 octet). Also, 8-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers or data bu ...
microprocessor (8-bit
register
Register or registration may refer to:
Arts, entertainment, and media
Music
* Register (music), the relative "height" or range of a note, melody, part, instrument, etc.
* ''Register'', a 2017 album by Travis Miller
* Registration (organ), ...
s and
data bus
In computer architecture, a bus (historically also called a data highway or databus) is a communication system that transfers data between components inside a computer or between computers. It encompasses both hardware (e.g., wires, optical ...
) with a
16-bit
16-bit microcomputers are microcomputers that use 16-bit microprocessors.
A 16-bit register can store 216 different values. The range of integer values that can be stored in 16 bits depends on the integer representation used. With the two ...
program counter
The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR), the instruction counter, or just part of the instruction sequencer, ...
and
address bus
In computer architecture, a bus (historically also called a data highway or databus) is a communication system that transfers data between components inside a computer or between computers. It encompasses both hardware (e.g., wires, optical ...
. The register set is small, with a single 8-bit
accumulator (A), two 8-bit
index register
An index register in a computer's central processing unit, CPU is a processor register (or an assigned memory location) used for pointing to operand addresses during the run of a program. It is useful for stepping through String (computer science ...
s (X and Y), an 8-bit status register (P), and a 16-bit program counter (PC). In addition to the single accumulator, the first 256 bytes of RAM, the "zero page" (
$0000
to
$00FF
), allow faster access through addressing modes that use an 8-bit memory address instead of a 16-bit address. The
stack
Stack may refer to:
Places
* Stack Island, an island game reserve in Bass Strait, south-eastern Australia, in Tasmania’s Hunter Island Group
* Blue Stack Mountains, in Co. Donegal, Ireland
People
* Stack (surname) (including a list of people ...
lies in the next 256 bytes, page one (
$0100
to
$01FF
), and cannot be moved or extended. The stack grows backwards with the
stack pointe
Stack may refer to:
Places
* Stack Island, an island game reserve in Bass Strait, south-eastern Australia, in Tasmania’s Hunter Island Group
* Blue Stack Mountains, in Co. Donegal, Ireland
People
* Stack (surname) (including a list of people ...
r (S) starting at $01FF and decrementing as the stack grows. It has a variable-length
instruction set
In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, s ...
, varying between one and three bytes per instruction.
The basic architecture of the 65C02 is identical to the original 6502, and can be considered a low-power implementation of that design. At 1 MHz, the most popular speed for the original 6502, the 65C02 requires only 20 mW, while the original uses 450 mW, a reduction of over twenty times. The manually optimized core and low power use is intended to make the 65C02 well suited for low power
system-on-chip
A system on a chip (SoC) is an integrated circuit that combines most or all key components of a computer or electronic system onto a single microchip. Typically, an SoC includes a central processing unit (CPU) with memory, input/output, and da ...
(SoC) designs.
A
Verilog
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits, with the highest level of abstraction being at the re ...
hardware description model is available for designing the W65C02S core into an
application-specific integrated circuit
An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficienc ...
(ASIC) or a
field-programmable gate array (FPGA). As is common in the semiconductor industry, WDC offers a development system, which includes a
developer board, an
in-circuit emulator
In-circuit emulation (ICE) is the use of a hardware device or in-circuit emulator used to debug the software of an embedded system. It operates by using a processor with the additional ability to support debugging operations, as well as to carr ...
(ICE) and a software development system.
The W65C02S–14 is the production version , and is available in
PDIP
In microelectronics, a dual in-line package (DIP or DIL) is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to a printed circuit board (PC ...
,
PLCC and
QFP
A quad flat package (QFP) is a surface-mounted integrated circuit package with "gull wing" leads extending from each of the four sides. Socketing such packages is rare and through-hole mounting is not possible. Versions ranging from 32 to 304 ...
packages. The maximum officially supported Ø2 (primary) clock speed is 14
MHz
The hertz (symbol: Hz) is the unit of frequency in the International System of Units (SI), often described as being equivalent to one event (or cycle) per second. The hertz is an SI derived unit whose formal expression in terms of SI base u ...
when operated at 5 volts, indicated by the –14 part number suffix (hobbyists have developed 65C02
homebrew systems that run significantly faster than the official rating). The "S" designation indicates that the part has a fully
static core
In integrated circuit design, static core generally refers to a microprocessor (MPU) entirely implemented in Dynamic logic (digital electronics)#Static versus dynamic logic, static logic. A static core MPU may be halted by stopping the Cloc ...
, which feature supports stopping the Ø2 clock in either phase with no loss of state. Typical microprocessors not implemented in CMOS have dynamic cores and will lose state (and thus crash) if they are not continuously clocked at a rate between some minimum and maximum specified values.
General logic features
* 8-bit
data bus
In computer architecture, a bus (historically also called a data highway or databus) is a communication system that transfers data between components inside a computer or between computers. It encompasses both hardware (e.g., wires, optical ...
.
* 16-bit
address bus
In computer architecture, a bus (historically also called a data highway or databus) is a communication system that transfers data between components inside a computer or between computers. It encompasses both hardware (e.g., wires, optical ...
(providing an address space of 64 KB).
* 8-bit
arithmetic logic unit
In computing, an arithmetic logic unit (ALU) is a Combinational logic, combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to a floating-point unit (FPU), which operates on ...
(ALU).
* 8-bit
processor register
A processor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-onl ...
s:
**
accumulator.
**
stack pointer
A stack register is a computer central processor register whose purpose is to keep track of a call stack. On an accumulator-based architecture machine, this may be a dedicated register. On a machine with multiple general-purpose registers, it m ...
.
**
index register
An index register in a computer's central processing unit, CPU is a processor register (or an assigned memory location) used for pointing to operand addresses during the run of a program. It is useful for stepping through String (computer science ...
s.
**
status register
A status register, flag register, or condition code register (CCR) is a collection of status Flag (computing), flag bits for a Central processing unit, processor. Examples of such registers include FLAGS register (computing), FLAGS register in the ...
.
* 16-bit
program counter
The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR), the instruction counter, or just part of the instruction sequencer, ...
.
* 69
instructions, implemented by 212
operation code
In computing, an opcode (abbreviated from operation code) is an enumerated value that specifies the operation to be performed. Opcodes are employed in hardware devices such as arithmetic logic units (ALUs), central processing units (CPUs), and s ...
s.
* 16
addressing mode
Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions ...
s, including
zero page
The zero page or base page is the block of memory at the very beginning of a computer's address space; that is, the page whose starting address is zero. The size of a page depends on the context, and the significance of zero page memory versus h ...
addressing.
Logic features
* Vector pull (
VPB
) output indicates when
interrupt vector
An interrupt vector table (IVT) is a data structure that associates a list of interrupt handlers with a list of interrupt requests in a table of interrupt vectors. Each entry of the interrupt vector table, called an interrupt vector, is the addre ...
s are being addressed.
* Memory lock (
MLB
) output indicates to other
bus master
In computing, bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate direct memory access (DMA) transactions. It is also referred to as first-party DMA, in contrast with third-party ...
s when a
read-modify-write instruction is being processed.
* WAit-for-Interrupt (
WAI
) and SToP (
STP
, stop-the-clock) instructions reduce power consumption, decrease
interrupt latency
In computing, interrupt latency refers to the delay between the start of an Interrupt Request (IRQ) and the start of the respective Interrupt Service Routine (ISR). For many operating systems, devices are serviced as soon as the device's interru ...
and enable synchronization with external events.
Electrical features
* Supply
voltage
Voltage, also known as (electrical) potential difference, electric pressure, or electric tension, is the difference in electric potential between two points. In a Electrostatics, static electric field, it corresponds to the Work (electrical), ...
specified at 1.71 V to 5.25 V.
* Current consumption (core) of 0.15 and 1.5
mA per
MHz
The hertz (symbol: Hz) is the unit of frequency in the International System of Units (SI), often described as being equivalent to one event (or cycle) per second. The hertz is an SI derived unit whose formal expression in terms of SI base u ...
at 1.89 V and 5.25 V respectively.
* Variable length instruction set, enabling code size optimization over fixed length instruction set processors, results in power savings.
* Fully
static core
In integrated circuit design, static core generally refers to a microprocessor (MPU) entirely implemented in Dynamic logic (digital electronics)#Static versus dynamic logic, static logic. A static core MPU may be halted by stopping the Cloc ...
allows stopping the clock to conserve power.
Clocking features
The W65C02S may be operated at any convenient supply voltage (V
DD) between 1.8 and 5 volts (±5%). The
data sheet
A datasheet, data sheet, or spec sheet is a document that summarizes the performance and other characteristics of a product, machine, component (e.g., an electronic component), material, subsystem (e.g., a power supply), or software in sufficie ...
AC characteristics table lists operational characteristics at 5 V at 14 MHz, 3.3 V or 3 V at 8 MHz, 2.5 V at 4 MHz, and 1.8 V at 2 MHz. This information may be an artifact of an earlier data sheet, as a graph indicates that typical devices are capable of operation at higher speeds than suggested by the AC characteristics table, and that reliable operation at 20 MHz should be readily attainable with V
DD at 5 volts, assuming the supporting hardware will allow it.
The W65C02S support for arbitrary clock rates allows it to use a clock that runs at a rate ideal for some other part of the system, such as 13.5 MHz (digital SDTV luma sampling rate), 14.31818 MHz (NTSC colour carrier frequency × 4), 14.75 MHz (PAL square pixels), 14.7456 (serial bit rate crystal), etc., as long as V
DD is sufficient to support the frequency. Designer
Bill Mensch
William David Mensch, Jr. (born February 9, 1945) is an American Electrical engineering, electrical engineer born in Quakertown, Pennsylvania. He was a major contributor to the design of the Motorola 6800 8-bit microprocessor and was part of the ...
has pointed out that F
MAX is affected by off-chip factors, such as the capacitive load on the microprocessor's pins. Minimizing load by using short signal tracks and fewest devices helps raise F
MAX. The PLCC and QFP packages have less pin-to-pin capacitance than the PDIP package, and are more economical in the use of
printed circuit board
A printed circuit board (PCB), also called printed wiring board (PWB), is a Lamination, laminated sandwich structure of electrical conduction, conductive and Insulator (electricity), insulating layers, each with a pattern of traces, planes ...
space.
WDC has reported that FPGA realizations of the W65C02S have been successfully operated at 200 MHz.
Comparison with the NMOS 6502
Basic architecture
Although the 65C02 can mostly be thought of as a low-power 6502, it also fixes several bugs found in the original and adds new instructions, addressing modes and features that can assist the programmer in writing smaller and faster-executing programs. It is estimated that the average 6502 assembly language program can be made 10 to 15 percent smaller on the 65C02 and see a similar improvement in performance, largely through avoided memory accesses through the use of fewer instructions to accomplish a given task.
Undocumented instructions removed
The original 6502 has 56 instructions, which, when combined with different addressing modes, produce a total of 151
opcode
In computing, an opcode (abbreviated from operation code) is an enumerated value that specifies the operation to be performed. Opcodes are employed in hardware devices such as arithmetic logic units (ALUs), central processing units (CPUs), and ...
s of the possible 256 8-bit opcode patterns. The remaining 105 unused opcodes are undefined, with the set of codes with low-order 4-bits with 3, 7, B or F left entirely unused, the code with low-order 2 having only a single opcode.
On the 6502, some of these leftover codes actually perform computation. Due to the way the 6502's instruction decoder works, simply setting certain bits in the opcode causes parts of the instruction processing to take place. Some of these opcodes immediately crash the processor, while other perform useful functions and were even given unofficial assembler mnemonics by some programmers.
The 65C02 adds new opcodes that use some of these previously undocumented instruction slots. For example, $FF is used for the new
BBS
instruction. Those which remain truly unused are equivalent to
NOP
s. 6502 programs using those opcodes will not work on the 65C02.
Bug fixes
A flaw that is present in all NMOS variants of the 6502 involves the jump instruction when using
indirect addressing
Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that are defined in a given instruction set architecture define how the machine language instructions ...
. In this addressing mode, the target address of the
JMP
instruction is fetched from memory, the jump vector, rather than being an operand to the
JMP
instruction. For example,
JMP ($1234)
would fetch the value in memory locations (least significant byte) and (most significant byte) and load those values into the
program counter
The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR), the instruction counter, or just part of the instruction sequencer, ...
, which would then cause the processor to continue execution at the address stored in the vector.
The flaw, which some consider a bug, appears when the vector address ends in , which is the boundary of a
memory page
A page, memory page, or virtual page is a fixed-length contiguous block of virtual memory, described by a single entry in a page table. It is the smallest unit of data for memory management in an operating system that uses virtual memory. Simila ...
. In this case,
JMP
will fetch the most significant byte of the target address from of the original page rather than of the new page. Hence
JMP ($12FF)
would get the least significant byte of the target address at and the most significant byte of the target address from rather than . The original 6502 documentation does not state that the address will cross pages in this fashion, so one cannot consider it to be a bug ''per-se''. But many 6502 users perceived this complication to be a weakness, so it was eliminated in the 65C02 at the cost of spending another cycle to update the pointer.
Another by-design weakness that was revised by popular demand, the state of the (D)ecimal flag in the NMOS 6502's status register is undefined after a
reset
Reset may refer to:
Film and television
* Reset (2015 film), ''Reset'' (2015 film), a 2015 French documentary film
* Reset (2017 film), ''Reset'' (2017 film), a 2017 Chinese film
* Reset (2024 film), ''Reset'' (2024 film), a 2024 Sri Lankan sh ...
or
interrupt
In digital computers, an interrupt (sometimes referred to as a trap) is a request for the processor to ''interrupt'' currently executing code (when permitted), so that the event can be processed in a timely manner. If the request is accepted ...
. This means programmers have to set the flag to a known value in order to avoid random errors caused by arithmetic operations performed in the mode other than the one intended, constititing software bugs. As a result, one finds a
CLD
instruction (CLear Decimal) in almost all 6502
interrupt handler
In computer systems programming, an interrupt handler, also known as an interrupt service routine (ISR), is a special block of code associated with a specific interrupt condition. Interrupt handlers are initiated by hardware interrupts, software ...
s, as well as early in the reset code. The 65C02 automatically clears this flag after pushing the status register onto the stack in response any interrupt or in response to a hardware reset, thus placing the processor back into binary arithmetic mode.
[ This usually saves a few bytes in the software and eliminates the possibility of a common programming mistake, at the cost of increasing the size of code that runs in decimal mode as programmers have to remember to ]SLD
in places they previously assumed it would still be set.
During decimal mode arithmetic, the NMOS 6502 will put the (N)egative, o(V)erflow and (Z)ero flags into officially undefined states. Programmers found that the CPU updates these three flags to reflect the result of underlying binary arithmetic, that is, the flags reflect a result computed prior to the processor performing decimal correction. In contrast, the 65C02 sets these flags according to the result of decimal arithmetic, at the cost of an extra clock cycle per arithmetic instruction. Some writers assert that the V flag on the 65C02 is still incorrect in decimal mode, but the flag may also be considered to be meaningless because decimal arithmetic is always unsigned.
When executing a read-modify-write (R-M-W) instruction, such as INC ''addr''
, all NMOS variants will do a double write on ''addr'', first rewriting the current value found at ''addr'' and then writing the modified value. This behavior can result in difficult-to-resolve bugs if ''addr'' is a hardware register. This may occur if the hardware is watching for changes to the value in the register and then performs an action, in this case, it will perform two actions, one with the original value and then again with the new value. The 65C02 instead performs a double read of ''addr'', followed by a single write.
When performing indexed addressing, if indexing crosses a page boundary all NMOS variants will read from an invalid address before accessing the correct address. As with a R-M-W instruction, this behavior can cause problems when accessing hardware registers via indexing. The 65C02 fixed this problem by performing a dummy read of the instruction opcode when indexing crosses a page boundary. However, this fix introduced a new bug that occurs when the base address is on an even page boundary (which means indexing will never cross into the next page). With the new bug, a dummy read is performed on the base address prior to indexing, such that LDA $1200,X
will do a dummy read on prior to the value of X being added to . Again, if indexing on hardware register addresses, this bug can result in undefined behavior.
If an NMOS 6502 is fetching a BRK (software interrupt) opcode at the same time a hardware interrupt occurs, the BRK will be ignored as the processor reacts to the hardware interrupt. The 65C02 correctly handles this situation by servicing the interrupt and then executing BRK.
New addressing modes
The 6502 has two indirect addressing modes which dereference through 16-bit addresses stored in page zero:
* Indexed indirect, e.g. LDA ($10,X)
, adds the X register to the given page zero address before reading the 16-bit vector. In this example, if X is 5, it reads the 16-bit address from location $15/$16. This is useful when there is an array of pointers in page zero.
* Indirect indexed LDA ($10),Y
adds the Y register to the 16-bit vector read from the given page zero address. For instance, if Y is 5, and contains the vector , This reads the value from . This performs pointer-offset addressing.
A downside of this model is that if indexing is not needed but the address is in the zero page, one of the index registers must still be set to zero and used in one of these instructions. The 65C02 adds a non-indexed indirect addressing mode, e.g. LDA ($10)
, to all instructions that can use indexed indirect and indirect indexed modes, freeing up the index registers.
The 6502's instruction has a unique (among 6502 instructions) addressing mode known as "absolute indirect" that reads a 16-bit value from a given memory address and then jumps to the address in that 16-bit value. For instance, if memory location holds $34 and holds $12, will read those two bytes, construct the value , and then jump to that location.
One common use for indirect addressing is to build branch table
A branch, also called a ramus in botany, is a Plant stem, stem that grows off from another stem, or when structures like veins in leaves are divided into smaller veins.
History and etymology
In Old English, there are numerous words for bra ...
s, a list of entry points for subroutine
In computer programming, a function (also procedure, method, subroutine, routine, or subprogram) is a callable unit of software logic that has a well-defined interface and behavior and can be invoked multiple times.
Callable units provide a ...
s that can be accessed using an index. For instance, a device driver
In the context of an operating system, a device driver is a computer program that operates or controls a particular type of device that is attached to a computer or automaton. A driver provides a software interface to hardware devices, enabli ...
might list the entry points for , , , etc in a table at . is the third entry, zero indexed, and each address requires 16-bits, so to call one would use something similar to . If the driver is updated and the subroutine code moves in memory, any existing code will still work as long as the table of pointers remains at .
The 65C02 adds the new "indexed absolute indirect" mode which eases the use of branch tables. This mode adds the value of the X register to the absolute address and takes the 16-bit address from the resulting location. For instance, to access the function from the table above, one stores 4 in X, then executes . This style of access makes accessing branch tables simpler as a single base address is used in conjunction with an 8-bit offset.[ The same can be achieved in the NMOS version using indexed indirect mode, but only if the table is in the zero page, a limited resource. Allowing these tables to be constructed outside zero page not only lessens the demand for this resource but also allows the tables to be placed in ROM.
]
New and modified instructions
In addition to the new addressing modes, the "base model" 65C02 also adds a set of new instructions.
* and with no parameters now increment or decrement the accumulator. This was an odd oversight in the original instruction set, which only included /, /, and /. Some assemblers use the alternate forms / or /.
* , STore Zero in ''addr'', replaces the need to ; and doesn't require changing the value of the accumulator. As this task is common in most programs, using can reduce code size, both by eliminating the as well as any code needed to save the value of the accumulator, typically a pair.
* ,,, push and pull the X and Y registers to and from the stack. Previously, only the accumulator and status register () had push and pull instructions. X and Y could be stacked only by moving them to the accumulator first with or , thereby changing the accumulator contents, then using PHA
.
* , branch always, operates like a but uses a 1-byte relative address like other branches (which all are conditional), saving a byte. The speed is often the same as the 3 cycle absolute unless a page is crossed which would make the version 1 cycle longer (4 cycles). As the address is relative, it is also useful when writing relocatable code.
Bit manipulation instructions
Both WDC and Rockwell contributed improvements to the bit testing and manipulation functions in the 65C02. WDC added new addressing modes to the BIT instruction that was present in the 6502, as well two new instructions for convenient manipulation of bit fields, a common activity in device drivers.
in the 65C02 adds immediate mode, zero page indexed by X and absolute indexed by X addressing. Immediate mode addressing is particularly convenient in that it is completely non-destructive. For example:
:LDA $1234
:BIT #%00010000
may be used in place of:
:LDA $1234
:AND #%00010000
The operation changes the value in the accumulator, so the original value loaded from $1234 is lost. Using leaves the value in the accumulator unchanged, so subsequent code can make additional tests against the original value, avoiding having to re-load the value from memory.
In addition to the enhancements of the instruction, WDC added two instructions designed to conveniently manipulate bit fields:
* TSB ''addr''
and TRB ''addr''
, Test and Set Bits and Test and Reset Bits.
:A mask in the accumulator (.A
) is logically ANDed with memory at , which location may be zero page or absolute. The Z flag in the status register is conditioned according to the result of the logical AND—no other status register flags are affected. Furthermore, bits in are set (TSB) or cleared (TRB) according to the mask in .A
. After the logical , TSB performs a logical of .A
with the memory byte and stores the result at , whereas TRB instead performs a logical of NOT .A
with the memory byte and stores the result at . In both cases, the Z flag in the status register indicates the result of .A AND ''addr''
before the content of is changed. The other flags are not affected. TRB and TSB thus replace a sequence of instructions, essentially combining the instruction with additional steps to save the computational changes, but without the additional steps affecting the flags, and without affecting the V flag as does.
Rockwell's changes added more bit manipulation instructions for any bit in zero page, to directly set or reset a bit with a 2-byte instruction, or to test and branch on a bit with a single 3-byte instruction. The new instructions were available from the start in Rockwell's R65C00 family, but were not part of the original 65C02 specification and not found in versions made by WDC or its other licensees. These were later copied back into the baseline design, and were available in later WDC versions.
Rockwell-specific instructions are:
* SMB''bit#'' ''zp''
and RMB''bit#'' ''zp''
. Set or Reset (clear) bit number ''bit#'' in zero page byte ''zp''.
:RMB and SMB are used to clear () or set () individual bits in a bit field, each replacing a sequence of three instructions. As and allow zero page addressing only, these instructions have limited usefulness and are primarily of value in systems in which device registers are present in zero page. The component of the instruction is part of the opcode and is often written as part of the mnemonic, such as SMB1 $12
which sets bit 1 in zero-page address (a/k/a address ). Some assemblers treat as part of the instruction's operand, e.g., SMB 1,$12
, which has the advantage of allowing it to be replaced by a variable name or calculated number.
* BBS''bit#'' ''zp'',''addr''
and BBR''bit#'' ''zp'',''addr''
. Branch on Bit Set/Reset.
:The same zero-page addressing and limitations as and apply, but these instructions test, rather than assign, the selected bit of the zero page byte ''zp'' and then branch to if that bit is clear () or set (). Also as with and above, the component of the instruction is often written as part of the mnemonic, such as BBS1 $12,''addr''
which branches to the address label if bit 1 of the byte at zero-page address is set. Again, some assemblers treat as part of the instruction's operand, e.g., BBS 1,$12,''addr''
, with the advantage of allowing it to be replaced by a variable name or calculated number.
Each of , , , and replaces a sequence of three instructions.
Low-power modes
In addition to the new commands above, WDC also added the STP
and WAI
instructions for supporting low-power modes.
, STop the Processor, halts all processing until a hardware reset is issued. This can be used to put a system to "sleep" and then rapidly "wake" (reactivate) it with a reset.
t has a similar effect, halting all processing, but this instruction resumes normal execution on the reception of an interrupt. Without this instruction, waiting for a hardware interrupt generally involves running a loop suspend the program until interrupt processing breaks out of the loop, sometimes known as "spinning
Spin or spinning most often refers to:
* Spin (physics) or particle spin, a fundamental property of elementary particles
* Spin quantum number, a number which defines the value of a particle's spin
* Spinning (textiles), the creation of yarn or thr ...
". This means the processor runs during the entire process, using power while doing (almost) nothing, even when no interrupts are occurring. In the 65C02, interrupt code can be written by having a followed immediately by a or to the handler. When the is encountered, processing stops and the processor goes into low-power mode. When an interrupt is received, the processor immediately executes the and handles the request.
This has the added advantage of slightly improving performance. In the spinning case, the interrupt might arrive in the middle of one of the loop's instructions, and to allow it to restart after returning from the handler, the processor spends three cycles to save its location. With , the processor enters the low-power state in a known location where all instructions are guaranteed to be complete, so when the interrupt arrives it cannot possibly interrupt an instruction and the interrupt response can be immediate. Plus, since the program expects the interrupt, the processor can safely continue without spending time saving state; the program is responsible to perform any necessary state-saving ''before'' the .
65SC02
The 65SC02 is a variant of the WDC 65C02 without bit instructions.
Uses
Home computers
* Apple IIc
The Apple IIc is a personal computer introduced by Apple Inc. shortly after the launch of the Macintosh 128K, original Macintosh in 1984. It is essentially a compact and portable version of the Apple IIe. The IIc has a built-in floppy disk driv ...
portable by Apple Computer
Apple Inc. is an American multinational corporation and technology company headquartered in Cupertino, California, in Silicon Valley. It is best known for its consumer electronics, software, and services. Founded in 1976 as Apple Computer Co ...
(NCR 1.023 MHz)
* Enhanced Apple IIe by Apple Computer (1.023 MHz)
* BBC Master
The BBC Master is a home computer released by Acorn Computers in early 1986. It was designed and built for the BBC, British Broadcasting Corporation (BBC) and was the successor to the BBC Micro, BBC Micro Model B. The Master 128 remained in prod ...
home/educational computer, by Acorn Computers Ltd
Acorn Computers Ltd. was a British computer company established in Cambridge, England in 1978 by Hermann Hauser, Christopher Curry (businessman), Chris Curry and Andy Hopper. The company produced a number of computers during the 1980s with asso ...
(2 MHz 65SC12 plus optional 4 MHz 65C102 second processor)
* Replica 1
The Replica 1 is a clone of the historic Apple I of 1976. It was designed by Vince Briel in 2003. It was the first Apple 1 clone to take advantage of more modern components, enabling the clone to be produced with cheaper and more widely availabl ...
by Briel Computers, a replica of the Apple I
The Apple Computer 1 (Apple-1), later known predominantly as the Apple I, is an 8-bit personal computer designed by Steve Wozniak and released by the Apple Computer Company (now Apple Inc.) in 1976. The company was initially formed to ...
hobbyist computer (1 MHz)
* Laser 128
The Laser 128 is an Apple II clone, released by VTech in 1986 and comparable to the Apple IIe and Apple IIc.
Description
VTech Laser 128 has 128 KB of RAM. Like the Apple IIc, it is a one-piece semi-portable design with a carrying handle and ...
series clones of Apple II
Apple II ("apple Roman numerals, two", stylized as Apple ][) is a series of microcomputers manufactured by Apple Computer, Inc. from 1977 to 1993. The Apple II (original), original Apple II model, which gave the series its name, was designed ...
* KIM-1 Modern Replica of the MOS/CBM KIM-1 by Briel Computing
Video game consoles
* Atari Lynx handheld (65SC02 @ ~4 MHz)
* PC Engine aka TurboGrafx-16 (HuC6280
The HuC6280 8-bit microprocessor is Japanese company Hudson Soft's improved version of the WDC 65C02 CPU, an upgraded CMOS version of the popular NMOS-based MOS Technology 6502 8-bit CPU, manufactured for Hudson by Seiko Epson and NEC. The most ...
@ 7.16 MHz)
* GameKing
GameKing is a brand of handheld game consoles, designed and developed by Timetop and manufactured by Guangzhou Panyu Gaoming Electronics Co., Ltd, (also known as GZ Daidaixing Tec.Electronics Co., Ltd.) in 2003, for the Hong Kong consumer market ...
handhelds (6 MHz) by Timetop
* Watara Supervision
The Watara Supervision, also known as the QuickShot Supervision in the UK, is a monochrome handheld game console, originating from Asia, and introduced in 1992 as a cut-price competitor for Nintendo's Game Boy. It came packaged with a game call ...
handhelds (KS5360 (65SC02 core) @ 4 MHz)
Other products
* TurboMaster accelerator cartridge for the Commodore 64
The Commodore 64, also known as the C64, is an 8-bit computing, 8-bit home computer introduced in January 1982 by Commodore International (first shown at the Consumer Electronics Show, January 7–10, 1982, in Las Vegas). It has been listed in ...
home computer (65C02 @ 4.09 MHz)
* Tube
Tube or tubes may refer to:
* ''Tube'' (2003 film), a 2003 Korean film
* "Tubes" (Peter Dale), performer on the Soccer AM television show
* Tube (band), a Japanese rock band
* Tube & Berger, the alias of dance/electronica producers Arndt Rör ...
-connected second processor for the Acorn BBC Micro home computer (65C02 @ 3 MHz)
* many dedicated chess computers
In computer chess, a chess engine is a computer program that analyzes chess or List of chess variants, chess variant positions, and generates a move or list of moves that it regards as strongest.
A chess software engine, engine is usually a Front ...
, e.g. Mephisto MMV, Novag Super Constellation, Fidelity Elite (4–20 MHz)
See also
* Interrupts in 65xx processors
The 65xx family of microprocessors, consisting of the MOS Technology 6502 and its derivatives, the WDC 65C02, WDC 65C802 and WDC 65C816, and CSG 65CE02, all handle interrupts in a similar fashion. There are three hardware interrupt signals comm ...
* CSG 65CE02
The CSG 65CE02 is an 8/16-bit microprocessor developed by Commodore Semiconductor Group in 1988. It is a member of the MOS Technology 6502 family, developed from the CMOS WDC 65C02 released by the Western Design Center in 1983.
Like the 65C02, ...
, a further enhanced version of the 65C02
Notes
References
Citations
Bibliography
*
*
Further reading
*
65C02 Datasheet
'; Western Design Center; 32 pages; 2018.
* ''Programming the 65816
The W65C816S (also 65C816 or 65816) is a 16-bit microprocessor (MPU) developed and sold by the Western Design Center (WDC). Introduced in 1985, the W65C816S is an enhanced version of the WDC 65C02 8-bit MPU, itself a CMOS enhancement of the vener ...
- including the 6502, 65C02, 65802''; 1st Ed; David Eyes and Ron Lichty; Prentice Hall; 636 pages; 1986; . (archive)
/small>
External links
65C02 webpage
- Western Design Center
- CPU World
– From Neil Parker's Apple II page
{{MOS CPU
65xx microprocessors
8-bit microprocessors