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FreeRTOS
FreeRTOS is a real-time operating system Kernel (operating system), kernel for embedded devices that has been ported to 40 microcontroller platforms. It is distributed under the MIT License. History The FreeRTOS kernel was originally developed by Richard Barry around 2003, and was later developed and maintained by Barry's company, Real Time Engineers Ltd. In 2017, the firm passed stewardship of the FreeRTOS project to Amazon Web Services (AWS). Barry continues to work on FreeRTOS as part of an AWS team. With the transition to Amazon control, subsequent releases of the project also switched licensing from GPL version 2 (with special exceptions for static linking to proprietary code outside the FreeRTOS kernel itself) to MIT. Implementation FreeRTOS is designed to be small and simple. It is mostly written in the C (programming language), C programming language to make it easy to port and maintain. It also comprises a few assembly language functions where needed, mostly in archite ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Nios II
Nios II is a 32-bit embedded processor architecture designed specifically for the Altera family of field-programmable gate array (FPGA) integrated circuits. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from digital signal processing (DSP) to system-control. Nios II is a successor to Altera's first configurable 16-bit embedded processor Nios, introduced in 2000. Intel announced the discontinuation of Nios II in 2023, with its successor being Nios V, based on the RISC-V architecture. Key features Like the original Nios, the Nios II architecture is a RISC soft-core architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. Unlike its predecessor it is a full 32-bit design: * 32 general-purpose 32-bit registers, * Full 32-bit instruction set, data path, and address space, * Single-instruction 32 × 32 multiply and divide ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM Architecture
ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer, RISC instruction set architectures (ISAs) for central processing unit, computer processors. Arm Holdings develops the ISAs and licenses them to other companies, who build the physical devices that use the instruction set. It also designs and licenses semiconductor intellectual property core, cores that implement these ISAs. Due to their low costs, low power consumption, and low heat generation, ARM processors are useful for light, portable, battery-powered devices, including smartphones, laptops, and tablet computers, as well as embedded systems. However, ARM processors are also used for desktop computer, desktops and server (computing), servers, including Fugaku (supercomputer), Fugaku, the world's fastest supercomputer from 2020 to 2022. With over 230 billion ARM chips produced, , ARM is the most widely used ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Atmel AVR
AVR is a family of microcontrollers developed since 1996 by Atmel, acquired by Microchip Technology in 2016. They are 8-bit RISC single-chip microcontrollers based on a modified Harvard architecture. AVR was one of the first microcontroller families to use on-chip flash memory for program storage, as opposed to Programmable read-only memory, one-time programmable ROM, EPROM, or EEPROM used by other microcontrollers at the time. AVR microcontrollers are used numerously as embedded systems. They are especially common in hobbyist and educational embedded applications, popularized by their inclusion in many of the Arduino line of open hardware development boards. The AVR 8-bit microcontroller architecture was introduced in 1997. By 2003, Atmel had shipped 500 million AVR flash microcontrollers. History The AVR architecture was conceived by two students at the Norwegian Institute of Technology (NTH), Alf-Egil Bogen and Vegard Wollan.Archived aGhostarchiveand thWayback Machine ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SHAKTI (microprocessor)
Shakti (stylized as SHAKTI) is an open-source initiative by the Reconfigurable Intelligent Systems Engineering (RISE) group at IIT Madras to develop the first indigenous industrial-grade processor. The aims of the Shakti initiative include building an open source production-grade processor, complete systems on a chip, microprocessor development boards, and a Shakti-based software platform. The main focus of the team is computer architecture research to develop SoCs, which are competitive with commercial offerings in the market in area, power, and performance. The source code for Shakti is open-sourced under the Modified BSD License. V. Kamakoti carried out the SHAKTI Microprocessor Project, at Prathap Subrahmanyam Centre for Digital Intelligence and Secure Hardware Architecture (Department of Computer Science & Engineering, IIT Madras). The Ministry of Electronics and Information Technology supports it through its Digital India RISC-V initiative. Processors Shakti processors ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
RISC-V
RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project commenced in 2010 at the University of California, Berkeley. It transferred to the RISC-V Foundation in 2015, and from there to RISC-V International, a Swiss non-profit entity, in November 2019. Similar to several other RISC ISAs, e.g. Amber (processor), Amber (ARMv2)(2001), SuperH#J_Core, J-Core(2015), OpenRISC(2000), or OpenSPARC(2005), RISC-V is offered under royalty-free open-source licenses. The documents defining the RISC-V instruction set architecture (ISA) are offered under a Creative Commons license or a BSD licenses, BSD License. Mainline support for RISC-V was added to the Linux 5.17 kernel in 2022, along with its toolchain. In July 2023, RISC-V, in its 64-bit computing, 64-bit variant called riscv64, was included as an official architecture of Linux distribution Debian, in its Debian version histor ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
PIC Microcontroller
PIC (usually pronounced as /pɪk/) is a family of microcontrollers made by Microchip Technology, derived from the PIC1640 originally developed by General Instrument's Microelectronics Division. The name PIC initially referred to ''Peripheral Interface Controller'',"MOS DATA 1976", General Instrument 1976 Databook and was subsequently expanded for a short time to include ''Programmable Intelligent Computer'', though the name PIC is no longer used as an acronym for any term. The first parts of the family were available in 1976; by 2013 the company had shipped more than twelve billion individual parts, used in a wide variety of embedded systems. The PIC was originally designed as a peripheral for the General Instrument CP1600, the first commercially available single-chip 16-bit microprocessor. To limit the number of pins required, the CP1600 had a complex highly- multiplexed bus which was difficult to interface with, so in addition to a variety of special-purpose peripherals ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Amazon Web Services
Amazon Web Services, Inc. (AWS) is a subsidiary of Amazon.com, Amazon that provides Software as a service, on-demand cloud computing computing platform, platforms and Application programming interface, APIs to individuals, companies, and governments, on a metered, pay-as-you-go basis. Clients will often use this in combination with elasticity (system resource), autoscaling (a process that allows a client to use more computing in times of high application usage, and then scale down to reduce costs when there is less traffic). These cloud computing web services provide various services related to networking, compute, storage, middleware, Internet of things, IoT and other processing capacity, as well as software tools via AWS server farms. This frees clients from managing, scaling, and patching hardware and operating systems. One of the foundational services is Amazon Elastic Compute Cloud (EC2), which allows users to have at their disposal a Virtualization, virtual Computer clus ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
H8 Family
The Hitachi H8 is a large family of 8-bit, 16-bit and 32-bit microcontrollers made by Renesas Technology, originating in the early 1990s within Hitachi Semiconductor. The original design, the H8/300, was an 8-bit processor that had a 16-bit registers and ALU that allowed some 16-bit operations. Two upgraded versions were introduced, the H8/300L that expanded the instructions to become a full 16-bit machine while being optimized for low cost, and the H8/300H which further expanded the registers to allow 32-bit operations and was optimized for low-power/high-performance roles. Many variations exist. The entire line was sold to Renesas in 2003. Renesas continues to sell the designs , but only to existing customers. An administrator on the Renesas user community boards commented in 2011 that there are no plans for further development of H8 based products. H8 was supported in the Linux kernel starting with version 4.2 but support was removed in version 5.19. For higher performanc ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SuperH
SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems. At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. Using smaller instructions had consequences: the processor register, register file was smaller and instructions were generally two-operand format. However for the market the SuperH was aimed at, this was a small price to pay for the improved memory and processor cache efficiency. Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. This allowed the machine code to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel 8051
The Intel MCS-51 (commonly termed 8051) is a single-chip microcontroller (MCU) series developed by Intel in 1980 for use in embedded systems. The architect of the Intel MCS-51 instruction set was John H. Wharton.. Intel's original versions were popular in the 1980s and early 1990s, and enhanced binary compatible derivatives remain popular today. It is a complex instruction set computer with separate memory spaces for program instructions and data. Intel's original MCS-51 family was developed using N-type metal–oxide–semiconductor ( NMOS) technology, like its predecessor Intel MCS-48, but later versions, identified by a letter C in their name (e.g., 80C51) use complementary metal–oxide–semiconductor ( CMOS) technology and consume less power than their NMOS predecessors. This made them more suitable for battery-powered devices. The family was continued in 1996 with the enhanced 8-bit MCS-151 and the 8/ 16/32-bit MCS-251 family of binary compatible microcontrollers. ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ESP32
ESP32 is a family of low-cost, energy-efficient microcontrollers that integrate both Wi-Fi and Bluetooth capabilities. These chips feature a variety of processing options, including the Tensilica Xtensa LX6 microprocessor available in both dual-core and single-core variants, the Xtensa LX7 dual-core processor, or a single-core RISC-V microprocessor. In addition, the ESP32 incorporates components essential for wireless data communication such as built-in antenna switches, an RF balun, power amplifiers, low-noise receivers, filters, and power-management modules. Typically, the ESP32 is embedded on device-specific printed circuit boards or offered as part of development kits that include a variety of GPIO pins and connectors, with configurations varying by model and manufacturer. The ESP32 was designed by Espressif Systems and is manufactured by TSMC using their 40 nm process. It is a successor to the ESP8266 microcontroller. Features Features of the ESP32 include the foll ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Freescale ColdFire
The NXP ColdFire is a microprocessor that derives from the Motorola 68000 family architecture, manufactured for embedded systems development by NXP Semiconductors. It was formerly manufactured by Freescale Semiconductor (formerly the semiconductor division of Motorola) which merged with NXP in 2015. Instruction set The ColdFire instruction set is "assembly source" compatible (by means of translation software available from the vendor) and not entirely object code compatible with the 68000. When compared to classic 68k hardware, the instruction set differs mainly in that it no longer has support for the binary-coded decimal (BCD) packed data format; it removes a number of other, less used instructions; and most instructions that are kept support fewer addressing modes. Also, floating point intermediates are 64 bits and not 80 bits as in the 68881 and 68882 coprocessors. The instructions are only 16, 32, or 48 bits long, a simplification compared to the 68000 series. Models In Fe ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
