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Q-Bus
The Q-bus, also known as the LSI-11 Bus, is one of several bus (computing), bus technologies used with Programmed Data Processor, PDP and VAX, MicroVAX computer systems previously manufactured by the Digital Equipment Corporation of Maynard, Massachusetts, Maynard, Massachusetts. The Q-bus is a less expensive version of Unibus using multiplexing so that address and data signals share the same wires. This allows both a physically smaller and less-expensive implementation of essentially the same functionality. Over time, the physical address range of the Q-bus was expanded from 16 to 18 and then 22 bits. Block transfer modes were also added to the Q-bus. Main features of the Q-bus The Q-bus is arranged as a series of Expansion card, modules installed in one or more Backplane, backplanes. Like the Unibus before it, the Q-bus uses: * ''Memory-mapped I/O'' * ''Byte addressing'' * A strict ''Master-slave (computers), master-slave'' relationship between devices on the bus * ''Asynchro ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
MicroVAX
The MicroVAX is a discontinued family of low-cost minicomputers developed and manufactured by Digital Equipment Corporation (DEC). The first model, the MicroVAX I, shipped in 1984. The series uses processors that implement the VAX instruction set architecture (ISA) and were succeeded by the VAX 4000. Many members of the MicroVAX family have corresponding VAXstation variants, which primarily differ by the addition of graphics hardware. The MicroVAX family supports Digital's OpenVMS, VMS, ULTRIX, and VAXELN operating systems. Prior to VMS V5.0, MicroVAX hardware required a dedicated version of VMS named MicroVMS. MicroVAX I The MicroVAX I, code-named ''Seahorse'', introduced in October 1984, was one of DEC's first VAX computers to use very-large-scale integration (VLSI) technology. The KA610 CPU module (also known as the KD32) contains two custom chips which implemented the Arithmetic-logic unit, ALU and Floating-point unit, FPU while Transistor-transistor logic, TTL chips were use ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Unibus
The Unibus was the earliest of several computer bus (computing), bus and backplane designs used with PDP-11 and early VAX systems manufactured by the Digital Equipment Corporation (DEC) of Maynard, Massachusetts, Maynard, Massachusetts. The Unibus was developed around 1969 by Gordon Bell and student Harold McFarland while at Carnegie Mellon University. The name refers to the unified nature of the bus; Unibus was used both as a system bus allowing the central processing unit to communicate with main memory, as well as a peripheral bus, allowing peripherals to send and receive data. Unifying these formerly separate busses allowed external devices to easily perform direct memory access (DMA) and made the construction of device drivers easier as control and data exchange was all handled through memory-mapped I/O. Unibus was physically large, which led to the introduction of Q-bus, which multiplexed some signals to reduce pin count. Higher performance PDP systems used Fastbus, essen ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
1801 Series CPU
The 1801 series CPUs were a family of 16-bit Soviet Union, Soviet microprocessors based on the indigenous microarchitecture cores, but binary compatible with Digital Equipment Corporation, DEC's PDP-11 machines. First released in 1980, various models and variants of the series were among the most popular Soviet microprocessors and dominated embedded systems and military applications of the 1980s. They were also used in widely different areas such as graphing calculators () and industrial CNCs (Elektronika NC series), but arguably their most well-known use was in several Soviet general-purpose minicomputer, mini- and microcomputer designs like the SM EVM, DVK, UKNC, and Elektronika BK, BK families. Due to being the CPU of the popular Elektronika BK home computer, used in its late years as a demoscene, demo machine, as well as the DVK micros that often offered a first glimpse into the UNIX world, this processor achieved something of a cult status among Soviet and then Russian progra ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Bus Arbitration
In computing, bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate direct memory access (DMA) transactions. It is also referred to as first-party DMA, in contrast with third-party DMA where a system DMA controller actually does the transfer. Some types of buses allow only one device (typically the CPU, or its proxy) to initiate transactions. Most modern bus architectures, such as PCI, allow multiple devices to bus master because it significantly improves performance for general-purpose operating systems. Some real-time operating systems prohibit peripherals from becoming bus masters, because the scheduler can no longer arbitrate for the bus and hence cannot provide deterministic latency. While bus mastering theoretically allows one peripheral device to directly communicate with another, in practice almost all peripherals master the bus exclusively to perform DMA to main memory. If multiple devices are able to ma ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Core Memory
Core or cores may refer to: Science and technology * Core (anatomy), everything except the appendages * Core (laboratory), a highly specialized shared research resource * Core (manufacturing), used in casting and molding * Core (optical fiber), the signal-carrying portion of an optical fiber * Core, the central part of a fruit * Hydrophobic core, the interior zone of a protein * Nuclear reactor core, a portion containing the fuel components * Pit (nuclear weapon) or core, the fissile material in a nuclear weapon * Semiconductor intellectual property core (IP core), is a unit of design in ASIC/FPGA electronics and IC manufacturing * Atomic core, an atom with no valence electrons * Lithic core, in archaeology, a stone artifact left over from toolmaking Geology and astrophysics * Core sample, in Earth science, a sample obtained by coring ** Ice core * Core, the central part of a galaxy; see Mass deficit * Core (anticline), the central part of an anticline or syncline * Pl ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Expansion Card
In computing, an expansion card (also called an expansion board, adapter card, peripheral card or accessory card) is a printed circuit board that can be inserted into an electrical connector, or expansion slot (also referred to as a bus slot) on a computer's motherboard (see also backplane) to add functionality to a computer system. Sometimes the design of the computer's case and motherboard involves placing most (or all) of these slots onto a separate, removable card. Typically such cards are referred to as a riser card in part because they project upward from the board and allow expansion cards to be placed above and parallel to the motherboard. Expansion cards allow the capabilities and interfaces of a computer system to be extended or supplemented in a way appropriate to the tasks it will perform. For example, a high-speed multi-channel data acquisition system would be of no use in a personal computer used for bookkeeping, but might be a key part of a system used for in ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Bubble Memory
Bubble memory is a type of non-volatile memory, non-volatile computer memory that uses a thin film of a magnetic material to hold small magnetized areas, known as ''bubbles'' or ''domains'', each storing one bit of data. The material is arranged to form a series of parallel tracks that the bubbles can move along under the action of an external magnetic field. The bubbles are read by moving them to the edge of the material, where they can be read by a conventional magnetic pickup, and then rewritten on the far edge to keep the memory cycling through the material. In operation, bubble memories are similar to delay-line memory systems. Bubble memory started out as a promising technology in the 1970s, offering performance similar to core memory, memory density similar to hard drives, and no moving parts. This led many to consider it a contender for a "universal memory" that could be used for all storage needs. The introduction of dramatically faster semiconductor memory chips in the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Vectored Interrupt
In computer science, a vectored interrupt is a processing technique in which the interrupting device directs the processor to the appropriate interrupt service routine. This is in contrast to a polled interrupt system, in which a single interrupt service routine must determine the source of the interrupt by checking all potential interrupt sources, a slow and relatively laborious process. Implementation Vectored interrupts are achieved by assigning each interrupting device a unique code, typically four to eight bits in length. When a device interrupts, it sends its unique code over the data bus In computer architecture, a bus (historically also called a data highway or databus) is a communication system that transfers data between components inside a computer or between computers. It encompasses both hardware (e.g., wires, optical ... to the processor, telling the processor which interrupt service routine to execute. References {{Reflist Computer architecture Interrupt ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Interrupt Priority Level
The interrupt priority level (IPL) is a part of the current system interrupt state, which indicates the interrupt requests that will currently be accepted. The IPL may be indicated in hardware by the registers in a programmable interrupt controller, or in software by a bitmask or integer value and source code of threads. Overview An integer based IPL may be as small as a single bit, with just two values: 0 (all interrupts enabled) or 1 (all interrupts disabled), as in the MOS Technology 6502. However, some architectures permit a greater range of values, where each value enables interrupt requests that specify a higher level, while blocking ones from the same or lower level. Assigning different priorities to interrupt requests can be useful in trying to balance system throughput versus interrupt latency. Some kinds of interrupts need to be responded to more quickly than others, but the amount of processing might not be large, so it makes sense to assign a higher priority to that ki ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Bus Arbiter
In computing, bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate direct memory access (DMA) transactions. It is also referred to as first-party DMA, in contrast with third-party DMA where a system DMA controller actually does the transfer. Some types of buses allow only one device (typically the CPU, or its proxy) to initiate transactions. Most modern bus architectures, such as PCI, allow multiple devices to bus master because it significantly improves performance for general-purpose operating systems. Some real-time operating systems prohibit peripherals from becoming bus masters, because the scheduler can no longer arbitrate for the bus and hence cannot provide deterministic latency. While bus mastering theoretically allows one peripheral device to directly communicate with another, in practice almost all peripherals master the bus exclusively to perform DMA to main memory. If multiple devices are able to ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
