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List Of Discontinued X86 Instructions
Instructions that have at some point been present as documented instructions in one or more x86 processors, but where the processor series containing the instructions are discontinued or superseded, with no known plans to reintroduce the instructions. Intel instructions i386 instructions The following instructions were introduced in the Intel 80386, but later discontinued: Itanium instructions These instructions are only present in the x86 operation mode of early Intel Itanium processors with hardware support for x86. This support was added in "Merced" and removed in "Montecito", replaced with software emulation. MPX instructions These instructions were introduced in 6th generation Intel Core "Skylake" CPUs. The last CPU generation to support them was the 9th generation Core "Coffee Lake" CPUs. Intel MPX adds 4 new registers, BND0 to BND3, that each contains a pair of addresses. MPX also defines a bounds-table as a 2-level directory/table data structure in memor ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Intel
Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, and Delaware General Corporation Law, incorporated in Delaware. Intel designs, manufactures, and sells computer components such as central processing units (CPUs) and related products for business and consumer markets. It is one of the world's List of largest semiconductor chip manufacturers, largest semiconductor chip manufacturers by revenue, and ranked in the Fortune 500, ''Fortune'' 500 list of the List of largest companies in the United States by revenue, largest United States corporations by revenue for nearly a decade, from 2007 to 2016 Fiscal year, fiscal years, until it was removed from the ranking in 2018. In 2020, it was reinstated and ranked 45th, being the List of Fortune 500 computer software and information companies, 7th-largest technology company in the ranking. It was one of the first companies listed on Nasdaq. Intel supplies List of I ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
General-purpose Register
A processor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. In computer architecture, registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900. Almost all computers, whether load/store architecture or not, load items of data from a larger memory into registers where they are used for arithmetic operations, bitwise operations, and other operations, and are manipulated or tested by machine instructions. Manipulated items are then often stored back to main memory, either by the same instruction or by a subsequent one. Modern processors use either static or dynamic random-access memory (RAM) as main memory, with the latter usually accessed via one or more cache levels. Processor registers are norm ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
AMD K6-III
The K6-III (code name: "Sharptooth") was an x86 microprocessor line manufactured by AMD that launched on February 22, 1999. The launch consisted of both 400 and 450 MHz models and was based on the preceding K6-2 architecture. Its improved 256 KB on-chip L2 cache gave it significant improvements in system performance over its predecessor the K6-2. The K6-III was the last processor officially released for desktop Socket 7 systems, however later mobile K6-III+ and K6-2+ processors could be run unofficially in certain socket 7 motherboards if an updated BIOS was made available for a given board. The Pentium III processor from Intel launched 6 days later. At its release, the fastest available desktop processor from Intel was the Pentium II 450 MHz, and in integer application benchmarks a 400 MHz K6-III was able to beat it as the fastest processor available for business applications. Just days later on February 28 Intel released the Pentium III "Katmai" line at speeds of ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
FP32
Single-precision floating-point format (sometimes called FP32 or float32) is a computer number format, usually occupying 32 bits in computer memory; it represents a wide dynamic range of numeric values by using a floating radix point. A floating-point variable can represent a wider range of numbers than a fixed-point variable of the same bit width at the cost of precision. A signed 32-bit integer variable has a maximum value of 231 − 1 = 2,147,483,647, whereas an IEEE 754 32-bit base-2 floating-point variable has a maximum value of (2 − 2−23) × 2127 ≈ 3.4028235 × 1038. All integers with seven or fewer decimal digits, and any 2''n'' for a whole number −149 ≤ ''n'' ≤ 127, can be converted exactly into an IEEE 754 single-precision floating-point value. In the IEEE 754 standard, the 32-bit base-2 format is officially referred to as binary32; it was called single in IEEE 754-1985. IEEE 754 specifies additional floating-point types, such as 64-bit base-2 ''double pr ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
K6-2
The K6-2 is an x86 microprocessor introduced by AMD on May 28, 1998, and available in speeds ranging from 266 to 550 MHz. An enhancement of the original K6, the K6-2 introduced AMD's 3DNow! SIMD instruction set and an upgraded system-bus interface called Super Socket 7, which was backward compatible with older Socket 7 motherboards. It was manufactured using a 250 nanometer process, ran at 2.2 volts, and had 9.3 million transistors. History The K6-2 was designed as a competitor to Intel's flagship processor, the significantly more expensive Pentium II. Performance of the two chips was similar: the previous K6 tended to be faster for general-purpose computing, while the Intel part was faster in x87 floating-point applications. To battle the Pentium II's dominance on floating point calculations the K6-2 was the first CPU to introduce a floating point SIMD instruction set (dubbed 3DNow! by AMD), which significantly boosted performance. However programs needed to be specifically ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
UMC Green CPU
The UMC Green CPU was an x86-compatible microprocessor produced by United Microelectronics Corporation, UMC, a Taiwanese semiconductor company, in the early- to mid-1990s. It was offered as an alternative to the Intel 80486 with which it was Pin compatibility, pin compatible, enabling it to be installed in most 80486 motherboards. All models had power management features intended to reduce electricity consumption. Models produced The UMC Green CPU was available with different features, physical characteristics and clock speeds. Some of which were only sold in limited quantities. Available models All models feature an 8 KB Processor cache, level 1 cache and operate at clock speeds of 25 MHz, 33 MHz, or 40 MHz. Functionally all models except U5D are identical and only differed in their intended application, voltage rating or physical packaging. The U5SD does not contain a floating point unit and is indistinguishable from other U5S chips in operation, though it ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
IBM 386SLC
The 386SLC is an Intel-licensed version of the 386SX (32-bit internal, 16-bit external, 24-bit memory addressing), developed and manufactured by IBM in 1991. It included power-management capabilities and an 8KB internal CPU cache, which enabled it to yield comparable performance to 386DX processors of the same clock speed, which were considerably more expensive. Known inside IBM as ''"Super Little Chip"'' for its initials, it was used in the IBM PS/2 35, 40 and 56 Series and in the IBM PS/ValuePoint 325T, but never gained much market share. This was mainly due to an agreement with Intel, in which IBM was not allowed to sell their CPUs if they were not part of a system or upgrade board. It was also marketed as an optional upgrade for 8086-equipped IBM PS/2 25 Series computers. Design and Technology Built with complementary metal oxide semiconductor (CMOS) technology, the IBM 386SLC had a 161-square millimeter die. It was available with clock speeds of 16, 20, and 25 MHz. The 25& ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
LOADALL
LOADALL is the common name for two different undocumented machine instructions of Intel 80286 and Intel 80386 processors, which allow access to areas of the internal processor state that are normally outside of the IA-32 API scope, like ''descriptor cache registers''. The LOADALL for 286 processors is encoded 0Fh 05h, while the LOADALL for 386 processors is 0Fh 07h. Both variants – as the name implies – load all CPU internal registers in one operation. LOADALL had the unique ability to set up the visible part of the segment registers (selector) independently of their corresponding cached part, allowing the programmer to bring the CPU into states not otherwise allowed by the official programming model. Usage As an example of the usefulness of these techniques, LOADALL can set up the CPU to allow access to all memory from real mode, without having to switch it into unreal mode (which requires switching into protected mode, accessing memory and finally switching back to real ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
X86 Debug Register
On the x86 architecture, a debug register is a register used by a processor for program debugging. There are six debug registers, named DR0...DR7, with DR4 and DR5 as obsolete synonyms for DR6 and DR7. The debug registers allow programmers to selectively enable various debug conditions associated with a set of four debug addresses. Two of these registers are used to control debug features. These registers are accessed by variants of the MOV instruction. A debug register may be either the source operand or destination operand. The debug registers are privileged resources; the MOV instructions that access them can only be executed at privilege level zero. An attempt to read or write the debug registers when executing at any other privilege level causes a general protection fault. DR0 to DR3 Each of these registers contains the linear address associated with one of four breakpoint conditions. Each breakpoint condition is further defined by bits in DR7. The debug address registers ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Microcode
In processor design, microcode serves as an intermediary layer situated between the central processing unit (CPU) hardware and the programmer-visible instruction set architecture of a computer. It consists of a set of hardware-level instructions that implement the higher-level machine code instructions or control internal finite-state machine sequencing in many digital processing components. While microcode is utilized in Intel and AMD general-purpose CPUs in contemporary desktops and laptops, it functions only as a fallback path for scenarios that the faster hardwired control unit is unable to manage. Housed in special high-speed memory, microcode translates machine instructions, state machine data, or other input into sequences of detailed circuit-level operations. It separates the machine instructions from the underlying electronics, thereby enabling greater flexibility in designing and altering instructions. Moreover, it facilitates the construction of complex multi-step inst ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
In-circuit Emulation
In-circuit emulation (ICE) is the use of a hardware device or in-circuit emulator used to debug the software of an embedded system. It operates by using a processor with the additional ability to support debugging operations, as well as to carry out the main function of the system. Particularly for older systems, with limited processors, this usually involved replacing the processor temporarily with a hardware emulator: a more powerful although more expensive version. It was historically in the form of bond-out processor which has many internal signals brought out for the purpose of debugging. These signals provide information about the state of the processor. More recently the term also covers JTAG-based hardware debuggers which provide equivalent access using on-chip debugging hardware with standard production chips. Using standard chips instead of custom bond-out versions makes the technology ubiquitous and low cost, and eliminates most differences between the development a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
AMD Élan
AMD Élan is a family of 32-bit embedded SoCs marketed by AMD based on x86 microprocessors. All of these products were backed with a long-term supply guarantee to meet the needs of embedded processors. However, when AMD acquired the Geode division from National Semiconductor in August 2003, the product was suddenly discontinued. The Élan processors saw a reasonable amount of use in the embedded world. In October 1993, AMD introduced the Am386SC processor, which integrated an Am386SXLV CPU core with a collection of PC/AT-compatible peripherals. This processor, marketed as Élan SC300 and Élan SC310, was the first in AMD's Élan series of SoCs. SC3xx family The SC300 and SC310 combines a 32-bit, x86 compatible, low-voltage 25 MHz or 33 MHz Am386SX CPU with memory controller, PC/AT peripheral controllers, real-time clock, PLL clock generators and ISA bus interface. SC300 integrates in addition two PCMCIA 2.1 slots and a CGA-compatible LCD controller. Power consump ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
