 |
Linux Process- And Task-management-related Software
Linux ( ) is a family of open source Unix-like operating systems based on the Linux kernel, an operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically packaged as a Linux distribution (distro), which includes the kernel and supporting system software and libraries—most of which are provided by third parties—to create a complete operating system, designed as a clone of Unix and released under the copyleft GPL license. Thousands of Linux distributions exist, many based directly or indirectly on other distributions; popular Linux distributions include Debian, Fedora Linux, Linux Mint, Arch Linux, and Ubuntu, while commercial distributions include Red Hat Enterprise Linux, SUSE Linux Enterprise, and ChromeOS. Linux distributions are frequently used in server platforms. Many Linux distributions use the word "Linux" in their name, but the Free Software Foundation uses and recommends the name "GNU/Linux" to emphasize the use and ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
 |
Tux (mascot)
Tux is a penguin character and the official mascot of the Linux kernel. Originally created as an entry to a Linux logo competition, Tux is the most commonly used icon for Linux, although different Linux distribution, Linux distributions depict Tux in various styles. The character is used in many other Linux programs and as a general symbol of Linux. History Origins The concept of the Linux brand character being a penguin came from Linus Torvalds, the creator of Linux. According to Jeff Ayers, Linus Torvalds had a "fixation for flightless, fat waterfowl" and Torvalds claims to have contracted "penguinitis" after being nibbled by a little penguin on a visit to the National Zoo & Aquarium in Canberra, Australia. Linus spoke at the 1994 AUUG Conference (5–9 Sept, Melbourne) as part of a "World Tour" to Belgium, Australia, Singapore and elsewhere, mentioning in ''Linux Journal'' he was bitten by a penguin at Canberra Zoo, not at Phillip Island, Victoria, by a (shy) wild penguin. I ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
|
M·CORE
M·CORE is a low-power, RISC-based microcontroller architecture developed by Motorola (subsequently Freescale, now part of NXP), intended for use in embedded systems. Introduced in late 1997, the architecture combines a 32-bit internal data path with 16-bit 16-bit microcomputers are microcomputers that use 16-bit microprocessors. A 16-bit register can store 216 different values. The range of integer values that can be stored in 16 bits depends on the integer representation used. With the two ... instructions, and includes a four-stage instruction pipeline. Initial implementations used a 360nm process and ran at 50 MHz. M·CORE processors employ a von Neumann architecture with shared program and data bus—executing instructions from within data memory is possible. Motorola engineers designed M·CORE to have low power consumption and high code density. [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
|
 |
SuperH
SuperH (or SH) is a 32-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Hitachi and currently produced by Renesas. It is implemented by microcontrollers and microprocessors for embedded systems. At the time of introduction, SuperH was notable for having fixed-length 16-bit instructions in spite of its 32-bit architecture. Using smaller instructions had consequences: the processor register, register file was smaller and instructions were generally two-operand format. However for the market the SuperH was aimed at, this was a small price to pay for the improved memory and processor cache efficiency. Later versions of the design, starting with SH-5, included both 16- and 32-bit instructions, with the 16-bit versions mapping onto the 32-bit version inside the CPU. This allowed the machine code to continue using the shorter instructions to save memory, while not demanding the amount of instruction decoding logic needed if they were completely ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
|
ESA/390
IBM Enterprise Systems Architecture is an instruction set architecture introduced by IBM as Enterprise Systems Architecture/370 (ESA/370) in 1988. It is based on the IBM System/370-XA architecture. It extended the dual-address-space mechanism introduced in later IBM System/370 models by adding a new mode in which general-purpose registers 1–15 are each associated with an access register referring to an address space, with instruction operands whose address is computed with a given general-purpose register as a base register will be in the address space referred to by the corresponding address register. The later Enterprise Systems Architecture/390 (ESA/390), introduced in 1990, added a facility to allow device descriptions to be read using channel commands and, in later models, added instructions to perform IEEE 754 floating-point operations and increased the number of floating-point registers from 4 to 16. Enterprise Systems Architecture is essentially a 32-bit archit ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
|
 |
RISC-V
RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project commenced in 2010 at the University of California, Berkeley. It transferred to the RISC-V Foundation in 2015, and from there to RISC-V International, a Swiss non-profit entity, in November 2019. Similar to several other RISC ISAs, e.g. Amber (processor), Amber (ARMv2)(2001), SuperH#J_Core, J-Core(2015), OpenRISC(2000), or OpenSPARC(2005), RISC-V is offered under royalty-free open-source licenses. The documents defining the RISC-V instruction set architecture (ISA) are offered under a Creative Commons license or a BSD licenses, BSD License. Mainline support for RISC-V was added to the Linux 5.17 kernel in 2022, along with its toolchain. In July 2023, RISC-V, in its 64-bit computing, 64-bit variant called riscv64, was included as an official architecture of Linux distribution Debian, in its Debian version histor ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
 |
PowerPC
PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple Inc., Apple–IBM–Motorola alliance, known as AIM alliance, AIM. PowerPC, as an evolving instruction set, has been named Power ISA since 2006, while the old name lives on as a trademark for some implementations of Power Architecture–based processors. Originally intended for personal computers, the architecture is well known for being used by Apple's desktop and laptop lines from 1994 until 2006, and in several videogame consoles including Microsoft's Xbox 360, Sony's PlayStation 3, and Nintendo's GameCube, Wii, and Wii U. PowerPC was also used for the Curiosity (rover), Curiosity and Perseverance (rover), Perseverance rovers on Mars and a variety of satellites. It has since become a niche architecture for personal computers, particularly with A ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
 |
PA-RISC
Precision Architecture reduced instruction set computer, RISC (PA-RISC) or Hewlett Packard Precision Architecture (HP/PA or simply HPPA), is a computer, general purpose computer instruction set architecture (ISA) developed by Hewlett-Packard from the 1980s until the 2000s. The architecture was introduced on 26 February 1986, when the HP 3000, HP 3000 Series 930 and HP 9000, HP 9000 Model 840 computers were launched featuring the first implementation, the TS1. HP stopped selling PA-RISC-based HP 9000 systems at the end of 2008 but supported servers running PA-RISC chips until 2013. PA-RISC was succeeded by the Itanium (originally IA-64) ISA, jointly developed by HP and Intel. History In the late 1980s, HP was building four series of computers, all based on Complex instruction set computer, CISC CPUs. One line was the IBM PC compatible Intel i286-based Vectra Series, started in 1986. All others were non-Intel systems. One of them was the HP Series 300 of Motorola 68000-based wor ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
 |
OpenRISC
OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community. The first (and only) architectural description is for the OpenRISC 1000 ("OR1k"), describing a family of 32-bit and 64-bit processors with optional floating-point arithmetic and vector processing support. The OpenRISC 1200 implementation of this specification was designed by Damjan Lampret in 2000, written in the Verilog hardware description language (HDL). The later mor1kx implementation, which has some advantages compared to the OR 1200, was designed by Julius Baxter and is also written in Verilog. Software simulators also exist which implement the OR1k specification. The hardware design was released under the GNU Lesser General Public License (LGPL), while the ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
|
Nios II
Nios II is a 32-bit embedded processor architecture designed specifically for the Altera family of field-programmable gate array (FPGA) integrated circuits. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from digital signal processing (DSP) to system-control. Nios II is a successor to Altera's first configurable 16-bit embedded processor Nios, introduced in 2000. Intel announced the discontinuation of Nios II in 2023, with its successor being Nios V, based on the RISC-V architecture. Key features Like the original Nios, the Nios II architecture is a RISC soft-core architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. Unlike its predecessor it is a full 32-bit design: * 32 general-purpose 32-bit registers, * Full 32-bit instruction set, data path, and address space, * Single-instruction 32 × 32 multiply and divide ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
|
|
MIPS Architecture
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, Inc. developed by MIPS Computer Systems, now MIPS Technologies, based in the United States. There are multiple versions of MIPS, including MIPS I, II, III, IV, and V, as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture. The MIPS architecture has several optional extensions: MIPS-3D, a simple set of floating-point SIMD instructions dedicated to 3D computer graphics; MDMX (MaDMaX), a more extensive i ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |