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Advanced Vector Extensions
Advanced Vector Extensions (AVX, also known as Gesher New Instructions and then Sandy Bridge New Instructions) are SIMD extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge microarchitecture shipping in Q1 2011 and later by AMD with the Bulldozer microarchitecture shipping in Q4 2011. AVX provides new features, new instructions, and a new coding scheme. AVX2 (also known as Haswell New Instructions) expands most integer commands to 256 bits and introduces new instructions. They were first supported by Intel with the Haswell microarchitecture, which shipped in 2013. AVX-512 expands AVX to 512-bit support using a new EVEX prefix encoding proposed by Intel in July 2013 and first supported by Intel with the Knights Landing co-processor, which shipped in 2016. In conventional processors, AVX-512 was introduced with Skylak ...
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Single Instruction, Multiple Data
Single instruction, multiple data (SIMD) is a type of parallel computer, parallel processing in Flynn's taxonomy. SIMD describes computers with multiple processing elements that perform the same operation on multiple data points simultaneously. SIMD can be internal (part of the hardware design) and it can be directly accessible through an instruction set architecture (ISA), but it should not be confused with an ISA. Such machines exploit Data parallelism, data level parallelism, but not Concurrent computing, concurrency: there are simultaneous (parallel) computations, but each unit performs exactly the same instruction at any given moment (just with different data). A simple example is to add many pairs of numbers together, all of the SIMD units are performing an addition, but each one has different pairs of values to add. SIMD is particularly applicable to common tasks such as adjusting the contrast in a digital image or adjusting the volume of digital audio. Most modern Cen ...
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Bit Manipulation Instruction Set
Bit manipulation instructions sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions in these sets are non-SIMD and operate only on general-purpose registers. There are two sets published by Intel: BMI (now referred to as BMI1) and BMI2; they were both introduced with the Haswell microarchitecture with BMI1 matching features offered by AMD's ABM instruction set and BMI2 extending them. Another two sets were published by AMD: ABM (''Advanced Bit Manipulation'', which is also a subset of SSE4a implemented by Intel as part of SSE4.2 and BMI1), and TBM (''Trailing Bit Manipulation'', an extension introduced with Piledriver-based processors as an extension to BMI1, but dropped again in Zen-based processors). ABM (Advanced Bit Manipulation) AMD was the first to introduce the instructions that now form Intel's BMI1 as part o ...
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GNU Compiler Collection
The GNU Compiler Collection (GCC) is a collection of compilers from the GNU Project that support various programming languages, Computer architecture, hardware architectures, and operating systems. The Free Software Foundation (FSF) distributes GCC as free software under the GNU General Public License (GNU GPL). GCC is a key component of the GNU toolchain which is used for most projects related to GNU and the Linux kernel. With roughly 15 million lines of code in 2019, GCC is one of the largest free programs in existence. It has played an important role in the growth of free software, as both a tool and an example. When it was first released in 1987 by Richard Stallman, GCC 1.0 was named the GNU C Compiler since it only handled the C (programming language), C programming language. It was extended to compile C++ in December of that year. Compiler#Front end, Front ends were later developed for Objective-C, Objective-C++, Fortran, Ada (programming language), Ada, Go (programming la ...
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GNU Assembler
The GNU Assembler, commonly known as gas or as, is the assembler developed by the GNU Project. It is the default back-end of GCC. It is used to assemble the GNU operating system and the Linux kernel, and various other software. It is a part of the GNU Binutils package. The GAS executable is named , the standard name for a Unix assembler. GAS is cross-platform, and both runs on and assembles for a number of different computer architectures. GAS is free software released under the GNU General Public License v3. History The first version of GAS was released in 1986–1987. It was written by Dean Elsner and supported the VAX architecture. General syntax GAS supports a general syntax that works for all of the supported architectures. The general syntax includes assembler directives and a method for commenting. The default syntax is AT&T syntax. Directives GAS uses assembler directives (also known as pseudo ops), which are keywords beginning with a period that behave similar ...
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Delphi (software)
Delphi is a general-purpose programming language and a software product that uses the Delphi dialect of the Object Pascal programming language and provides an integrated development environment (IDE) for rapid application development of desktop, mobile, web, and console software, currently developed and maintained by Embarcadero Technologies. Delphi's compilers generate native code for Microsoft Windows, macOS, iOS, Android and Linux ( x64). Delphi includes a code editor, a visual designer, an integrated debugger, a source code control component, and support for third-party plugins. The code editor features Code Insight (code completion), Error Insight (real-time error-checking), and refactoring. The visual forms designer has the option of using either the Visual Component Library (VCL) for pure Windows development or the FireMonkey (FMX) framework for cross-platform development. Database support is a key feature and is provided by FireDAC (Database Access Components). D ...
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Free Pascal
Free Pascal Compiler (FPC) is a compiler for the closely related programming-language dialects Pascal and Object Pascal. It is free software released under the GNU General Public License, witexception clausesthat allow static linking against its runtime libraries and packages for any purpose in combination with any other software license. It supports its own Object Pascal dialect, as well as the dialects of several other Pascal family compilers to a certain extent, including those of Borland Pascal (named "Turbo Pascal" until the 1990 version 6), Borland (later Embarcadero) Delphi, and some historical Macintosh compilers. The dialect is selected on a per-unit (module) basis, and more than one dialect can be used per program. It follows a '' write once, compile anywhere'' philosophy and is available for many CPU architectures and operating systems (see Targets). It supports inline assembly language and includes an internal assembler capable of parsing several dialects such a ...
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Absoft Fortran Compilers
Absoft Corporation was an American software company active from 1980 to 2022. They were best known for their set of Fortran compilers for Microsoft Windows, Apple Macintosh, and Linux operating systems. The compilers are source code compatible across platforms. * Absoft Pro Fortran on 64-bit platforms supports both 32-bit and 64-bit executables; the user selects which format that the compiler will produce. * Linux compilers are available in either 32-bit or 64-bit versions. The 32-bit version produces only 32-bit executables. All are bundled with a graphical debugger and an integrated development environment. Single thread and parallel Thread_(computing)#Single-threaded_vs_multithreaded_programs, multithread support is controlled by the user and includes five optimization levels, OpenMP, Speed Math levels 0 through 9, and other advanced capabilities. On September 30, 2022, Absoft ceased operations. History Origins: Absoft FORTRAN 77 for MC68000 Systems The principals of A ...
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Zhaoxin
Zhaoxin (Shanghai Zhaoxin Semiconductor Co., Ltd.; , ) is a fabless semiconductor company, created in 2013 as a joint venture between VIA Technologies and the Shanghai Municipal Government. The company manufactures x86-compatible desktop and laptop CPUs. The term '' Zhào xīn'' means ''million core''.In China 兆 can mean either short-scale million (1e6) or trillion (1e12). However, for IT-related topics 兆 always means mega/million in mainland China. The processors are created mainly for the Chinese market: the venture is an attempt to reduce the Chinese dependence on foreign technology. Background ''Zhaoxin'' is a joint venture between VIA Technologies and the Shanghai Municipal Government. In 2021 it was reported that VIA has a 14.75% shareholding in the company. China has a domestic policy to "replace all foreign hardware and software from its public infrastructure with homegrown solutions" by 2023 (the so-called 3–5–2 policy). VIA holds an x86 license which allows ...
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VIA Technologies
VIA Technologies, Inc. () is a Taiwanese manufacturer of integrated circuits, mainly motherboard chipsets, CPUs, and memory. It was once the world's largest independent manufacturer of motherboard chipsets. As a fabless semiconductor company, VIA conducts research and development of its chipsets in-house, then subcontracts the actual (silicon) manufacturing to third-party merchant foundries such as TSMC. VIA is also the parent company of VIA Labs Inc. (VLI, ). As an independently traded subsidiary, VLI develops and markets USB 3, USB 4, USB Type-C, and USB PD controllers for computer peripherals and mobile devices. History The company was founded in 1987, in Fremont, California, USA by Cher Wang. In 1992, it was decided to move the headquarters to Taipei, Taiwan in order to establish closer partnerships with the substantial and growing IT manufacturing base in Taiwan and neighbouring China. In 1999, VIA acquired most of Cyrix, then a division of National Semiconductor. Th ...
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XOP Instruction Set
The XOP (''eXtended Operations'') instruction set, announced by AMD on May 1, 2009, is an extension to the 128-bit SSE core instructions in the x86 and AMD64 instruction set for the Bulldozer processor core, which was released on October 12, 2011. However AMD removed support for XOP from Zen (microarchitecture) onward. The XOP instruction set contains several different types of vector instructions since it was originally intended as a major upgrade to SSE. Most of the instructions are integer instructions, but it also contains floating point permutation and floating point fraction extraction instructions. See the index for a list of instruction types. History XOP is a revised subset of what was originally intended as SSE5. It was changed to be similar but not overlapping with AVX, parts that overlapped with AVX were removed or moved to separate standards such as FMA4 (floating-point vector multiply–accumulate) and CVT16 ( Half-precision floating-point conversion imp ...
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IEEE Micro
''IEEE Micro'' is a bimonthly peer-reviewed scientific journal published by the IEEE Computer Society covering small systems and semiconductor chips, including integrated circuit processes and practices, project management, development tools and infrastructure, as well as chip design and architecture, empirical evaluations of small system and IC technologies and techniques, and human and social aspects of system development. Editors-in-chief The following people are or have been editor-in-chief: * 2024–present: Hsien-Hsin Sean Lee * 2019–2023: Lizy Kurian John * 2015–2018: Lieven Eeckhout * 2011–2014: Erik R. Altman * 2007–2010: David H. Albonesi * 2003–2006: Pradip Bose * 1999–2001: Ken Sakamura * 1995–1998: Steve Diamond * 1991–1994: Dante Del Corso * 1987–1990: Joe Hootman * 1985–1987: James J. Farrell III * 1983–1984: Peter Rony and Tom Cain * 1980–1982: Richard C. Jaeger External links * Micro Micro may refer to: Measurement * ...
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Tiger Lake
Tiger Lake is Intel's codename for the 11th generation Intel Core mobile processors based on the Willow Cove Core microarchitecture, manufactured using Intel's third-generation 10 nm process node known as 10SF ("10 nm SuperFin"). Tiger Lake replaces the Ice Lake family of mobile processors, representing an optimization step in Intel's process–architecture–optimization model. Tiger Lake processors launched on September 2, 2020. They are part of the Tiger Lake-U family (however, they end with the suffixes -G4 and -G7 instead of -U) and include dual-core and quad-core 9 W (7–15 W) TDP and 15 W (12–28 W) TDP models. They power 2020 Intel Evo laptops. The quad-core 96 EU die measures 13.6 × 10.7 mm (146.1 mm2), which is 19.2% wider than the 11.4 × 10.7 mm (122.5 mm2) quad-core 64 EU Ice Lake die. The 8-core 32 EU die used in Tiger Lake-H is around 190 mm2. Laptops based on Tiger Lake started to sell in October 2020. The Tiger Lake-H35 processors wer ...
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