The Info List - System-on-chip

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A system on a chip or system on chip (SoC or SOC) is an integrated circuit (also known as an "IC" or "chip") that integrates all components of a computer or other electronic systems. It may contain digital, analog, mixed-signal, and often radio-frequency functions – all on a single substrate. SoCs are very common in the mobile computing market because of their low power consumption.[1] A typical application is in the area of embedded systems. SoC integrates a microcontroller (or microprocessor) with advanced peripherals like graphics processing unit (GPU), Wi-Fi
module, or coprocessor. If the definition of a microcontroller is a system that integrates a microprocessor with peripheral circuits and memory, the SoC is to a microcontroller what a microcontroller is to processors, remembering that the SoC does not necessarily contain built-in memory. In general, there are three distinguishable types of SoCs. SoCs built around a microcontroller, SoCs built around a microprocessor (this type can be found in mobile phones), and specialized SoCs designed for specific applications that do not fit into the above two categories. A separate category may be Programmable SoC (PSoC), where some of the internal elements are not predefined and can be programmable in a manner analogous to a field-programmable gate array (FPGA) or a complex programmable logic device (CPLD). When it is not feasible to construct a SoC for a particular application, an alternative is a system in package (SiP) comprising a number of chips in a single package. When produced in large volumes, SoC is more cost-effective than SiP because its packaging is simpler.[2] Another option, as seen for example in higher-end cell phones, is package on package stacking during board assembly. The SoC includes processors and numerous digital peripherals, and comes in a ball grid package with lower and upper connections. The lower balls connect to the board and various peripherals, with the upper balls in a ring holding the memory buses used to access NAND flash and DDR2 RAM. Memory
packages could come from multiple vendors.

AMD Am286ZX/LX, SoC based on 80286


1 Structure 2 Design flow 3 Fabrication 4 Benchmarks 5 See also 6 References 7 Further reading 8 External links


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Microcontroller-based system on a chip

A typical SoC consists of:

a microcontroller, microprocessor or digital signal processor (DSP) core – multiprocessor SoCs (MPSoC) having more than one processor core memory blocks including a selection of ROM, RAM, EEPROM
and flash memory timing sources including oscillators and phase-locked loops peripherals including counter-timers, real-time timers and power-on reset generators external interfaces, including industry standards such as USB, FireWire, Ethernet, USART, SPI analog interfaces including ADCs and DACs voltage regulators and power management circuits

A bus – either proprietary or industry-standard such as the AMBA bus from ARM Holdings
ARM Holdings
– connects these blocks. DMA controllers route data directly between external interfaces and memory, bypassing the processor core and thereby increasing the data throughput of the SoC. Design flow[edit]

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System-on-a-chip design flow

A SoC consists of both the hardware, described above, and the software controlling the microcontroller, microprocessor or DSP cores, peripherals and interfaces. The design flow for a SoC aims to develop this hardware and software in parallel. Most SoCs are developed from pre-qualified hardware blocks for the hardware elements described above, together with the software drivers that control their operation. Of particular importance are the protocol stacks that drive industry-standard interfaces like USB. The hardware blocks are put together using CAD tools; the software modules are integrated using a software-development environment. Once the architecture of the SoC has been defined, any new hardware elements are written in an abstract language termed RTL which defines the circuit behaviour. These elements are connected together in the same RTL language to create the full SoC design. Chips are verified for logical correctness before being sent to foundry. This process is called functional verification and it accounts for a significant portion of the time and energy expended in the chip design life cycle (although the often quoted figure of 70% is probably an exaggeration).[3] With the growing complexity of chips, hardware verification languages like SystemVerilog, SystemC, e, and OpenVera are being used. Bugs found in the verification stage are reported to the designer. Traditionally, engineers have employed simulation acceleration, emulation and/or an FPGA prototype
FPGA prototype
to verify and debug both hardware and software for SoC designs prior to tapeout. With high capacity and fast compilation time, acceleration and emulation are powerful technologies that provide wide visibility into systems. Both technologies, however, operate slowly, on the order of MHz, which may be significantly slower – up to 100 times slower – than the SoC's operating frequency. Acceleration and emulation boxes are also very large and expensive at over US$1 million. FPGA
prototypes, in contrast, use FPGAs directly to enable engineers to validate and test at, or close to, a system’s full operating frequency with real-world stimuli. Tools such as Certus[4] are used to insert probes in the FPGA RTL that make signals available for observation. This is used to debug hardware, firmware and software interactions across multiple FPGAs with capabilities similar to a logic analyzer. In parallel, the hardware elements are grouped and passed through a process of logic synthesis, during which performance constraints, such as operational frequency and expected signal delays, are applied. This generates a logical netlist which is a file describing the circuit as a collection of connected silicon gate elements from a library provided by the silicon manufacturer. This netlist is used as the basis for the physical design (place and route) flow to convert the designers' intent into the polygonal design of the SoC. Throughout this conversion process, the design is analysed with static timing modelling, simulation and other tools to ensure that it meets the specified operational parameters such as frequency, power consumption and dissipation, functional integrity vs. the RTL and electrical integrity. When all known bugs have been rectified and these have been re-verified and all physical design checks are done, the physical design files describing each layer of the chip are sent to the foundry's mask shop where a full set of glass lithographic masks will be etched. These are sent to the wafer fabrication plant to create the SoC dice before packaging and testing. Fabrication[edit]

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SoCs can be fabricated by several technologies, including:

Full custom Standard cell Field-programmable gate array
Field-programmable gate array

SoC designs usually consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. And with fewer packages in the system, assembly costs are reduced as well. However, like most VLSI
designs, the total cost is higher for one large chip than for the same functionality distributed over several smaller chips, because of lower yields and higher non-recurring engineering costs. Benchmarks[edit] SoC research and development often compares many options. Benchmarks, such as COSMIC,[5] are developed to help such evaluations. See also[edit]

List of system-on-a-chip suppliers PSoC Electronic design automation Post-silicon validation Single-board computer Network on a chip ARM architecture Socionext


^ Pete Bennett, EE Times. "The why, where and what of low-power SoC design." December 2, 2004. Retrieved July 28, 2015. ^ EE Times. "The Great Debate: SOC vs. SIP." March 21, 2005. Retrieved July 28, 2015. ^ EE Times. "Is verification really 70 percent?." June 14, 2004. Retrieved July 28, 2015. ^ Brian Bailey, EE Times. "Tektronix hopes to shake up ASIC prototyping." October 30, 2012. Retrieved July 28, 2015. ^ "COSMIC Heterogeneous Multiprocessor Benchmark Suite"

Further reading[edit]

Badawy, Wael; Jullien, Graham A., eds. (2003). System-on-Chip
for Real-Time Applications. Kluwer international series in engineering and computer science, SECS 711. Boston: Kluwer Academic Publishers. ISBN 9781402072543. OCLC 50478525.  465 pages. Furber, Stephen B. (2000). ARM system-on-chip architecture. Boston: Addison-Wesley. ISBN 0-201-67519-6. 

External links[edit]

SOCC Annual IEEE International SOC Conference Baya free SoC platform assembly and IP integration tool

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CPU technologies


Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (modified) Dataflow TTA Cellular Artificial neural network

Machine learning Deep learning Neural processing unit (NPU)

Convolutional neural network Load/store architecture Register memory architecture Endianness FIFO Zero-copy NUMA HUMA HSA Mobile computing Surface computing Wearable computing Heterogeneous computing Parallel computing Concurrent computing Distributed computing Cloud computing Amorphous computing Ubiquitous computing Fabric computing Cognitive computing Unconventional computing Hypercomputation Quantum computing Adiabatic quantum computing Linear optical quantum computing Reversible computing Reverse computation Reconfigurable computing Optical computing Ternary computer Analogous computing Mechanical computing Hybrid computing Digital computing DNA computing Peptide computing Chemical computing Organic computing Wetware computing Neuromorphic computing Symmetric multiprocessing
Symmetric multiprocessing
(SMP) Asymmetric multiprocessing
Asymmetric multiprocessing
(AMP) Cache hierarchy Memory

ISA types



x86 z/Architecture ARM MIPS Power Architecture
Power Architecture
(PowerPC) SPARC Mill Itanium
(IA-64) Alpha Prism SuperH V850 Clipper VAX Unicore PA-RISC MicroBlaze RISC-V

Word size

1-bit 2-bit 4-bit 8-bit 9-bit 10-bit 12-bit 15-bit 16-bit 18-bit 22-bit 24-bit 25-bit 26-bit 27-bit 31-bit 32-bit 33-bit 34-bit 36-bit 39-bit 40-bit 48-bit 50-bit 60-bit 64-bit 128-bit 256-bit 512-bit Variable


Instruction pipelining

Bubble Operand forwarding

Out-of-order execution

Register renaming

Speculative execution

Branch predictor Memory
dependence prediction


Parallel level


Bit-serial Word

Instruction Pipelining

Scalar Superscalar


Thread Process





Temporal Simultaneous (SMT) (Hyper-threading) Speculative (SpMT) Preemptive Cooperative Clustered Multi-Thread (CMT) Hardware scout

Flynn's taxonomy



Addressing mode

CPU performance

Instructions per second (IPS) Instructions per clock (IPC) Cycles per instruction (CPI) Floating-point operations per second (FLOPS) Transactions per second (TPS) Synaptic Updates Per Second (SUPS) Performance per watt Orders of magnitude (computing) Cache performance measurement and metric

Core count

Single-core processor Multi-core processor Manycore processor


Central processing unit
Central processing unit
(CPU) GPGPU AI accelerator Vision processing unit (VPU) Vector processor Barrel processor Stream processor Digital signal processor
Digital signal processor
(DSP) I/O processor/DMA controller Network processor Baseband processor Physics processing unit
Physics processing unit
(PPU) Coprocessor Secure cryptoprocessor ASIC FPGA FPOA CPLD Microcontroller Microprocessor Mobile processor Notebook processor Ultra-low-voltage processor Multi-core processor Manycore processor Tile processor Multi-chip module
Multi-chip module
(MCM) Chip stack multi-chip modules System on a chip
System on a chip
(SoC) Multiprocessor system-on-chip (MPSoC) Programmable System-on-Chip
(PSoC) Network on a chip (NoC)


Execution unit (EU) Arithmetic logic unit
Arithmetic logic unit
(ALU) Address generation unit
Address generation unit
(AGU) Floating-point unit
Floating-point unit
(FPU) Load-store unit (LSU) Branch predictor Unified Reservation Station Barrel shifter Uncore Sum addressed decoder (SAD) Front-side bus Back-side bus Northbridge (computing) Southbridge (computing) Adder (electronics) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory
management unit (MMU) Input–output memory management unit
Input–output memory management unit
(IOMMU) Integrated Memory
Controller (IMC) Power Management Unit (PMU) Translation lookaside buffer
Translation lookaside buffer
(TLB) Stack engine Register file Processor register Hardware register Memory
buffer register (MBR) Program counter Microcode
ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three-dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed-signal integrated circuit Power management integrated circuit Quantum circuit Logic gate

Combinational logic Sequential logic Emitter-coupled logic
Emitter-coupled logic
(ECL) Transistor–transistor logic
Transistor–transistor logic
(TTL) Glue logic

Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor

Power management

APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating

Hardware security

Non-executable memory (NX bit) Memory
Protection Extensions ( Intel
MPX) Intel
Secure Key Hardware restriction (firmware) Software Guard Extensions ( Intel
SGX) Trusted Execution Technology Trusted Platform Module
Trusted Platform Module
(TPM) Secure cryptoprocessor Hardware security module Hengzhi chip


History of general-purpose CPUs

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Single-board computer
Single-board computer
& Single-board microcontroller


Arduino Arndale Board Asus Tinker Board Banana Pi BeagleBoard Cotton Candy CHIP Cubieboard Dragonboard Edison Galileo Gumstix Hawkboard IGEPv2 Nvidia Drive Nvidia Jetson ODROID OLinuXino PandaBoard Pine64 Parallella Rascal Raspberry Pi Snowball Tiva-C LaunchPad UDOO



Allwinner Ax Exynos i.MX K3V3 MT Nomadik NovaThor OMAP Rockchip Qualcomm Snapdragon Tegra WonderMedia




Atom Jaguar-based Puma-based Quark


Apache Hadoop Linaro

Comparison of single-board computers

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Programmable logic



Logic block

CPLD EPLD PLA PAL GAL PSoC Reconfigurable computing


Soft microprocessor Circuit underutilization










Accellera Actel Achronix AMD Aldec Altera Atmel Cadence Cypress Duolog Forte Intel Lattice National Mentor Graphics Microsemi Signetics Synopsys

Magma Virage Logic

Texas Instruments Tabula Xilinx



iCE Stratix Virtex


Quartus Xilinx
ISE Xilinx
Vivado ModelSim VTR Simulators



ARC LEON LatticeMico8 MicroBlaze PicoBlaze Nios Nios II


JOP LatticeMico32 OpenCores OpenRISC