Stanford MIPS

MIPS, an acronym for Microprocessor without Interlocked Pipeline Stages, was a research project conducted by John L. Hennessy at Stanford University between 1981 and 1984. MIPS investigated a type of instruction set architecture (ISA) now called reduced instruction set computer (RISC), its implementation as a microprocessor with very large scale integration (VLSI) semiconductor technology, and the effective exploitation of RISC architectures with optimizing compilers. MIPS, together with the IBM 801 and Berkeley RISC, were the three research projects that pioneered and popularized RISC technology in the mid-1980s. In recognition of the impact MIPS made on computing, Hennessey was awarded the IEEE John von Neumann Medal in 2000 by the Institute of Electrical and Electronics Engineers (IEEE) (shared with David A. Patterson), the Eckert–Mauchly Award in 2001 by the Association for Computing Machinery, the Seymour Cray Computer Engineering Award in 2001 by the IEEE Computer Society, and, again with David Patterson, the Turing Award in 2017 by the ACM.

The project was initiated in 1981 in response to reports of similar projects at IBM (the 801) and the University of California, Berkeley (the RISC). MIPS was conducted by Hennessy and his graduate students until its conclusion in 1984. Hennessey founded MIPS Computer Systems in the same year to commercialize the technology developed by the project. In 1985, MIPS Computer Systems announced a new ISA, also called MIPS, and its first implementation, the R2000 microprocessor. The commercial MIPS ISA, and its implementations went on to be widely used, appearing in embedded computers, personal computers, workstations, servers, and supercomputers. As of May 2017, the commercial MIPS ISA is owned by Imagination Technologies, and is used mainly in embedded computers. In the late 1980s, a follow-up project called MIPS-X was conducted by Hennessy at Stanford.

The MIPS ISA was based on a 32-bit word. It supported 32-bit addressing, and was word-addressed. It was a load/store architecture—all references to memory used load and store instructions that copied data between the main memory and 32 general-purpose registers (GPRs). All other instructions, such as integer arithmetic, operated on the GPRs. It possessed a basic instruction set consisting of instructions for control flow, integer arithmetic, and logical operations. To minimize pipeline stalls, all instructions except for load and store had to be executed in one clock cycle. There were no instructions for integer multiplication or division, or operations for floating-point numbers. The architecture exposed all hazards caused by the five-stage pipeline with delay slots. The compiler scheduled instructions to avoid hazards resulting in incorrect computation whilst simultaneously ensuring that the generated code minimized execution time. MIPS instructions are 16 or 32 bit long. The decision to expose all hazards was motivated by the desire to maximize performance by minimizing critical paths, which interlock circuits lengthened. Instructions were packed into 32-bit ''instruction words'' (as MIPS is word-addressed). A 32-bit instruction word could contain two 16-bit operations. These were included to reduce the size of machine code. The MIPS microprocessor was implemented in NMOS logic.

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{{RISC-based processor architectures

MIPS architecture
Instruction set architectures
32-bit microprocessors
American inventions
Stanford University