In
electrical engineering, noise margin is the maximum voltage amplitude of extraneous
signal
In signal processing, a signal is a function that conveys information about a phenomenon. Any quantity that can vary over space or time can be used as a signal to share messages between observers. The '' IEEE Transactions on Signal Processing' ...
that can be algebraically added to the noise-free worst-case input level without causing the output voltage to deviate from the allowable logic voltage level. It is commonly used in at least two contexts as follows:
*In
communications system engineering, noise margin is the ratio by which the signal exceeds the minimum acceptable amount. It is normally measured in
decibels.
*In a
digital circuit, the noise margin is the amount by which the signal exceeds the threshold for a proper '0' or '1'. For example, a digital circuit might be designed to swing between 0.0 and 1.2
volt
The volt (symbol: V) is the unit of electric potential, electric potential difference (voltage), and electromotive force in the International System of Units (SI). It is named after the Italian physicist Alessandro Volta (1745–1827).
Defin ...
s, with anything below 0.2 volts considered a '0', and anything above 1.0 volts considered a '1'. Then the noise margin for a '0' would be the amount that a signal is below 0.2 volts, and the noise margin for a '1' would be the amount by which a signal exceeds 1.0 volt. In this case noise margins are measured as an absolute voltage, not a ratio. Noise margins for CMOS chips are usually much greater than those for TTL because the V
OH min is closer to the power supply voltage and V
OL max is closer to zero.
**Real digital inverters do not instantaneously switch from a logic high (1) to a logic low (0), there is some capacitance. While an inverter is transitioning from a logic high to low, there is an undefined region where the voltage cannot be considered high or low. This is considered a noise margin. There are two noise margins to consider: Noise margin high (N
MH) and noise margin low (N
ML). N
MH is the amount of voltage between an inverter transitioning from a logic high (1) to a logic low (0) and vice versa for N
ML. The equations are as follows: N
MH ≡ V
OH - V
IH and N
ML ≡ V
IL - V
OL.
Typically, in a CMOS inverter V
OH will equal V
DD and V
OL will equal the ground potential, as mentioned above.
***V
IH is defined as the highest input voltage at which the slope of the
voltage transfer characteristic (VTC) is equal to -1,
[{{Cite book, url=https://archive.org/details/introductiontodi00gopa, title=Introduction to digital electronic circuits, last=Gopal., first=Gopalan, K., date=1996, publisher=Irwin, isbn=0256120897, location=Chicago, oclc=33664747, url-access=registration] where the VTC is the plot of all valid output voltages vs. input voltages. Similarly, V
IL is defined as the lowest input voltage where slope of the VTC is equal to -1.
In practice, noise margins are the amount of noise, that a logic circuit can withstand.
Noise margins are generally defined so that positive values ensure proper operation, and negative margins result in compromised operation, or outright failure.
See also
*
Digital circuit
*
Signal integrity
*
Substrate coupling
*
ITU G.992.1
*
signal-to-noise ratio
*
signal
In signal processing, a signal is a function that conveys information about a phenomenon. Any quantity that can vary over space or time can be used as a signal to share messages between observers. The '' IEEE Transactions on Signal Processing' ...
References
External links
DMT a DSL monitoring and downstream noise margin tweaking program.
MIT PDF of a PowerPoint Presentation on for Digital Noise Margin.
Electronic engineering
Electronic design
Electronic design automation
Integrated circuits