C4004 (Intel).jpg

The Intel 4004 is a 4-bit central processing unit (CPU) released by Intel Corporation in 1971. Sold for US$60, it was the first commercially produced microprocessor, and the first in a long line of Intel CPUs.

The 4004 was the first significant example of large scale integration, showcasing the superiority of the MOS silicon gate technology (SGT). Compared to the incumbent technology, the SGT integrated on the same chip area twice the number of transistors with five times the operating speed. This step-function increase in performance made possible a single-chip CPU, replacing the existing multi-chip CPUs. The innovative 4004 chip design served as a model on how to use the SGT for complex logic and memory circuits, thus accelerating the adoption of the SGT by the world’s semiconductor industry. The developer of the original SGT at Fairchild was Federico Faggin who designed the first commercial integrated circuit (IC) that used the new technology, proving its superiority for analog/digital applications (Fairchild 3708 in 1968). He later used the SGT at Intel to obtain the unprecedented integration necessary to make the first single chip microprocessor.

The project traces its history to 1969, when Busicom Corp. approached Intel to design a family of seven chips for an electronic calculator, three of which constituted a CPU specialized for making different calculating machines. The CPU was based on data stored on shift-registers and instructions stored on ROM (read only memory). The complexity of the three-chip CPU logic design led Marcian Hoff to propose a more conventional CPU architecture based on data stored on RAM (random access memory). This architecture was much simpler and more general-purpose and could potentially be integrated into a single chip, thus reducing the cost and improving the speed. Design began in April 1970 under the direction of Federico Faggin aided by Masatoshi Shima who contributed to the architecture and later to the logic design. The first delivery of a fully operational 4004 was in March 1971 to Busicom for its 141-PF printing calculator engineering prototype (now displayed in the Computer History Museum in Mountain View, California). General sales began July 1971.

A number of innovations developed by Faggin while working at Fairchild Semiconductor allowed the 4004 to be produced on a single chip. The main concept was the use of the self-aligned gate, made of polysilicon rather than metal, which allowed the components to be much closer together and work at higher speed. To make the 4004 possible, Faggin also developed the "bootstrap load", considered unfeasible with silicon gate, and the "buried contact" that allowed the silicon gates to be connected directly to the source and drain of the transistors without the use of metal. Together, these innovations doubled the circuit density, and thus halved cost, allowing a single chip to contain 2300 transistors and run five times faster than designs using the previous MOS technology with aluminum gates.

The 4004 design was later improved by Faggin as the Intel 4040 in 1974. The Intel 8008 and 8080 were unrelated designs in spite of the similar naming.

History

Original concept

In April 1969, Busicom approached Intel to produce a new design for an electronic calculator. They based their design on the architecture of the 1965 Olivetti Programma 101, one of the world's first tabletop programmable calculators. The key difference was that the Busicom design would use integrated circuits to replace the printed circuit boards filled with individual components, and solid-state shift registers for memory instead of the costly magnetostriction wire in the 101.

In contrast to earlier calculator designs, Busicom had developed a general-purpose processor concept with the goal of introducing it in a low-end desktop printing calculator, and then using the same design for other roles like cash registers and automatic teller machines. The company had already produced a calculator using TTL small scale integration logic ICs and were interested in having Intel reduce the chip count using Intel's medium scale integration (MSI) techniques.

Intel assigned the recently hired Marcian Hoff, employee number 12, to act as the liaison between the two companies. In late June, three engineers from Busicom travelled to Intel to introduce the design, Masatoshi Shima and his colleagues Masuda and Takayama. Although he had only been assigned to liaise with the engineers, Hoff began studying the concept. Their initial proposal had seven ICs, program control, arithmetic unit (ALU), timing, program ROM, shift registers for temporary memory, printer controller and input/output control.

Hoff became concerned that the number of chips and the required interconnections between them would make Busicom's price goals impossible to meet. Combining the chips would reduce the complexity and cost. He was also concerned that the still-small Intel would not have enough design staff to make seven separate chips at the same time. He raised these concerns with upper management, and Bob Noyce, the CEO, told Hoff he would support a different approach if it seemed feasible.

Simplified design

A key concept in the Busicom design was that the program control and ALU were not aimed specifically at the calculator market, it was the program in ROM that turned it into a calculator. The original idea was that the company could use the same chips with different amounts of shift register RAM and program ROM to produce a range of calculating machines. Hoff was struck by how closely the Busicom's instruction set architecture matched that of general-purpose computers. He began to consider whether a truly general-purpose processor could be made cheaply enough to be used in a calculator. When later asked where he got the ideas for the architecture of the first microprocessor, Hoff related that Plessey, "a British tractor company", had donated a minicomputer to Stanford, and he had "played with it some" while he was there. Tadashi Sasaki attributes the idea to break the calculator into four parts to an unnamed woman from the Nara Women's College present at a brainstorming meeting that was held in Japan prior to his first meeting with Intel.

Another development that allowed this design to be made practical was Intel's work on the earliest dynamic RAM (DRAM) chips. Shift registers at that time were among the only low-cost read and write memory devices. They do not allow random access, instead, with every clock pulse they move the stored data one cell along a chain of cells. The time to retrieve any given data, one byte for instance, is a function of the clock speed and the number of cells in a chain. If the processor had to wait for each bit to cycle through the register the resulting effective speed would be far too low to be practical. DRAM, on the other hand, allowed random access to any data they stored, while also having roughly double the capacity and thus being less expensive.

Finally, Hoff noticed that much of the complexity of the program control chip was due to every instruction being implemented separately. He suggested that the chip instead support subroutine calls and instructions be implemented as subroutines where possible. The application naturally suggested a 4-bit design, as this allowed direct manipulation of binary coded decimal (BCD) values used by calculators. Hoff worked on the overall design concept through July and August 1969 but found the Busicom executives seemed uninterested in his proposal.

Mazor joins

Unknown to Hoff, the Busicom team were extremely interested in his proposal. However, there were a number of specific issues that they were concerned about. One key issue was that certain routines like decimal adjust and keyboard handling would use large amounts of ROM space if implemented as subroutines. Another was that the design did not feature any sort of interrupt so dealing with real-time events would be difficult. Finally, storing the numbers as 4-bit BCD would require additional memory to store the sign and decimal place.

In September 1969, Stanley Mazor joined Intel from Fairchild. Hoff and Mazor quickly came up with solutions to the Busicom concerns. To address the complexity of the subroutines, originally solved in Busicom's design using one byte macroinstructions and complex decoder circuitry, Mazor developed a 20-byte long interpreter that executed the same macroinstructions. Shima suggested adding a new interrupt that would be triggered by a pin, thereby allowing the keyboard to be interrupt driven. He also modified the Branch Back (return from subroutine) instruction to clear the accumulator.

To reach the price goals, it was important that the chip be as small as possible and use the fewest number of leads. As data was 4-bits and the address space was 12-bits (4096 bytes), there was no way direct access could be arranged with anything fewer than about 24-pins. This was not small enough, so the design would use a 16-pin dual in-line package (DIP) layout and use multiplexing of a single set of 4 lines. This meant specifying which address in ROM to access required three clock cycles, and another two to read it from memory. Running at 1 MHz would allow it to perform math on the BCD values at about 80 microseconds per digit.

The result of the discussions between Intel and Busicom was an architecture that reduced the 7-chip Busicom design to a 4-chip Intel proposal composed of CPU, ROM, RAM and I/O (input-output) devices. Such proposal was presented to a visiting team of Busicom executives in October 1969. They agreed the new concept was superior, and gave Intel the go-ahead to begin development. Hoff was upset to learn that the contract assigned all rights to the design to Busicom, in spite of it being designed entirely within Intel. The team then left for Japan, but Shima remained in California until December, developing many of the subroutines.

Faggin joins

Neither Hoff nor Mazor, who worked in the Applications Research group, had experience designing the actual silicon, and the design group was already overworked with the development of memory devices. In April 1970, Leslie Vadász, who ran the MOS design group, hired Federico Faggin from Fairchild Semiconductor to take over the project. Faggin had already made a name for himself by leading the entire development of the MOS silicon gate technology and the design of the first commercial integrated circuit (IC) made with it. The new technology was going to change the entire semiconductor market.

Integrated circuits consist of a number of individual components like transistors and resistors that are produced by mixing the underlying silicon with "dopants". This is normally accomplished by heating the chip in the presence of a chemical gas, which diffuses into the surface. Previously, the individual components were connected together to make a circuit using aluminium wires deposited on the surface. As aluminum melts at 600 degrees and silicon at 1000, the traces typically had to be deposited as the last step, which often complicated the production cycle.

In 1967, Bell Labs released a paper about making MOS transistors with self-aligned gates made of silicon rather than metal. These devices, however, were a proof-of-concept and could not be used to make ICs. Faggin and Tom Klein had taken what was a curiosity and developed the entire process technology needed to fabricate reliable ICs. Faggin also designed and produced the Fairchild 3708, the first IC made with SGT, first sold at the end of 1968, and featured on the cover of Electronics (29 September 1969). in 1968. The silicon gate technology also reduced the leakage current by more than 100 times, making possible sophisticated dynamic circuits like DRAMs (dynamic random access memories). It also allowed the highly-doped silicon used for the gates to form the interconnections, greatly improving the circuit density of random-logic ICs like microprocessors.

This technique meant the interconnections could be performed at any time in the process. More importantly, the wiring was deposited using the same equipment that made the rest of the components. This meant that the slight differences in layout between different machine types was eliminated. Previously the interconnects had to be much larger than required in order to ensure the aluminum touched the silicon components which would be offset due to inaccuracies in the machinery. With this issue eliminated, the circuits could be placed much closer together, immediately doubling the density of the components, and thus reducing their cost by the same amount. Additionally, the aluminum wiring acted as capacitors which limited the signal speed; removing these allowed the chips to run at faster speeds.

At Intel, Faggin began design of the new processor using this self-aligned gate process. Only days after Faggin joined the company Intel, Shima arrived from Japan and was disappointed to learn that no work on the project had taken place since he left in December, and expressed his concern original schedule was now impossible. Faggin responded by working well into the night every day, and Shima stayed on for another six months to help. Additional advances were needed to reach the required circuit density. One of these advances was the use of "buried contacts" that allowed the silicon connecting wires to be directly connected to the components another was figuring out how to make adding "bootstrap loads" with silicon gate. as part of one of the masking steps, eliminating one step from the processing. Without these two additional innovations by Faggin, Hoff’s architecture could not have been realized in a single chip.

Into production

Intel's chip-naming scheme at that time used a four-digit number for each component. The first digit indicated the process technology used, the second digit indicated the generic function, and the last two digits specified the sequential number in the development of that component type. Using this convention, the chips would have been known as the 1302, 1105, 1507, and 1202. Faggin felt this would obscure the fact that they formed a coherent set, and decided to name them as the "4000 family". The four chips were the following: the 4001, 256-byte 4-bit ROM; the 4002, DRAM with four 20-nibble registers; the 4003, I/O with a 10-bit static shift register with serial and parallel outputs; and the 4004 CPU. A fully expanded system could support 16 4001's for a total of 4 kB of ROM, 16 4002's for a total of 1,280 nibbles (640) bytes of RAM, and an unlimited number of 4003's. The 4003's were connected to programmable input and output pins on the 4001 and to output pins on the 4002, not directly to the CPU.

With the design complete, Shima returned to Japan to begin building a prototype of the calculator. The first wafers of the 4001 were processed in October 1970, followed by the 4003 and 4002 in November. The 4002 proved to have a minor problem that was easily corrected. The first 4004s arrived at the end of December, and were completely non-functional. Probing the chip, Faggin found that the buried-contact fabrication step had been left out. A second run was fabricated in January 1971 and the 4004 worked perfectly except for two minor problems. That same month Shima sent Intel the final code for the 4001 ROMs, since the Busicom’s calculator design was now complete. It consisted of one 4004, two 4002, three 4003, and four 4001 chips. An additional 4001 supplied the optional square root function and the final design was produced in March.

Faggin was sending samples of these chips to Shima as they arrived. In April, they learned the calculator prototype was operational. Later that month, Shima sent Intel the final masks for the 4001 ROMs, the design was now complete. It consisted of one 4004, two 4002, three 4003, and four 4001 chips. An additional 4001 supplied the optional square root function. One final change was added after Faggin found a frustrating problem in the 4001 that only occurred when the chips were hot. Adding a new register decoder circuit was Faggin's solution. The same problem was also seen in the 4002 and the same same solution was used. Production began in quantity in August 1971.

Marketing the 4004

During a call to Shima, Faggin learned that Busicom was in financial difficulty and would likely fail if the chip price was not reduced. Faggin then convinced Noyce to lower the price in exchange for releasing Intel from the exclusivity agreement. In May 1971 Busicom agreed to this, on the condition that it not be used for any other calculator project and that Intel would repay their $60,000 development costs. With this change of marketing focus name of the chip family name was changed to MCS-4, short for Micro Computer System, 4-bit.

Intel management was skeptical that their sales team could explain the product to their customers. As Intel was now successful in the memory market, they were concerned the 4004 might confuse the market and were hesitant to advertise it. They feared current Intel customers might view the new product as competition, purchasing memory from competitors instead. Hoff and Mazor were also concerned that the design's limitations would make it less interesting to users who were accustomed to the new 16-bit minicomputers entering the market at that time.

This all changed in the summer of 1971, when Ed Gelbach, formerly of Texas Instruments, took over the marketing department and immediately began plans to publicly announce the product. This took place in the November 1971 when Intel ran ads "Announcing a new era of integrated electronics," first appearing in the 15 November edition of ''Electronic News''.

The 8008

The 4004 became the first commercial microprocessor available for general use. This was almost not the case.

In December 1969, Intel was approached by Computer Terminal Corporation (CTC) to produce a custom bipolar memory chip for a computer terminal they were designing, the Datapoint 2200. Mazor and Hoff considered their CPU design and concluded it was not much more complicated than the 4004, and that it could be implemented as a single-chip 8-bit CPU. A few weeks before they hired Faggin, in March 1970 Intel hired Hal Feeney to design the 8008, at that time called 1201 following Intel's naming convention. However, CTC decided to initially proceed with a conventional TTL implementation of their CPU and the project was lowered in priority. Feeney was assigned to other projects and ultimately ended up helping Faggin with testing the 4000 family chips.

In January 1971, Feeney was reassigned back to the 1201 under Faggin’s supervision and production chips were available in March 1972. In May, Hoff and Mazor went on a speaking tour to introduce the two CPU designs around the USA. The tradeoffs between the two designs were that with the 4004 and its memory and I/O chips it was much easier to build a complete computer system while the 8008 was more flexible, had a larger 16 kB address space, and offered more instructions. A significant difference is that while a minimal 4004 system could be built using only two chips, one 4004 and one 4001 (256-byte ROM), the 8008 would require at least 20 additional TTL components for interfacing with memory and I/O functions

The two designs found themselves being used in different roles. The 4004 was used where the cost of implementation was the major concern, and became widely used in embedded controllers for applications like microwave ovens or traffic lights and similar roles. The 8008 instead found itself mostly used in user-programmable applications, such as computer terminals, microcomputers and similar roles. This split in functionality remains to this day, with the former being known as a microcontroller.

Contemporaneous CPU chips

Three other CPU chip designs were produced at about the same time: the Four-Phase Systems AL1, done in 1969; the MP944, completed in 1970 and used in the F-14 Tomcat fighter jet; and the Texas Instruments TMS-0100 chip, announced on 17 September 1971. The MP944 was a collection of six chips forming a single processor unit. The TMS0100 chip was presented as a "calculator on a chip" with the original designation TMS1802NC. This chip contains a very primitive CPU and can only be used to implement various simple four-function calculators. It is the precursor of the TMS1000, introduced in 1974, which is considered the first microcontroller—i.e., a computer on a chip containing not only the CPU, but also ROM, RAM, and I/O functions. The MCS-4 family of four chips developed by Intel, of which the 4004 is the CPU or microprocessor, was far more versatile and powerful than the single-chip TMS1000, allowing the creation of a variety of small computers for various applications.

Zilog, the first company entirely dedicated to microprocessors and microcontrollers, was started by Federico Faggin and Ralph Ungermann at the end of 1974.

Note:
If the word “microprocessor” is used to specify a general-purpose CPU integrated into a single chip, none of the so-called microprocessor chips that existed prior to the 4004 deserve that name.

Description

The 4004 employs an 10 μm process silicon-gate enhancement-load pMOS technology on a and can execute approximately instructions per second; a single instruction cycle is The original clock rate design goal was 1 MHz, the same as the IBM 1620 Model I.

The Intel 4004 was fabricated using masks produced by physically cutting each pattern at 500x magnification on a large sheet of Rubylith photo-reducing it, and repeating, a process made obsolete by current computer graphic design capabilities.

For the purpose of testing the produced chips, Faggin developed a tester for silicon wafers of MCS-4 family that was itself driven by 4004 chip. The tester also served as a proof for the management that Intel 4004 microprocessor could be used not only in calculator-like products, but also for control applications.

The 4004 includes functions for direct low-level control of memory-chip selection and I/O, which are not normally handled by the microprocessor; however, its functionality is limited in that it cannot execute code from RAM and is limited to whatever instructions are provided in ROM (or an independently loaded RAM working as ROM—in either case, the processor is itself unable to write or transfer data into an executable memory space). The RAM and ROM parts chips also unusual in their integration of I/O functions together with their primary memory function. this partitioning significantly reduced the minimum part count in an MCS-4 system, but required inclusion of a certain amount of processor-like logic on the memory chips themselves to accept, decode and execute relatively high-level data-transfer instructions.

The standard arrangement for a 4004 system is anything up to 16 × 4001 ROM chips (in a single bank) and 16 × 4002 RAM chips (in four banks of four), which together provide the 4 KB program storage, 1024 + 256 nibbles of data/status storage, plus 64 output and 64 input/output external data/control lines (which can themselves be used to operate, e.g. a 4003). Intel's MCS-4 documentation, however, claims that up to 48 ROM and RAM chips (providing up to 192 external control lines) "in any combination" can be connected to the 4004 "with simple gating hardware", but declines to give any further detail or examples of how this would actually be achieved.

Technical specifications

* Maximum clock rate is 740  kHz. The 4004 had this maximum clock rating upon its initial 1971 release.
* Instruction cycle time: minimum 10.8 μs (8 clock cycles per machine cycle).
* Instruction execution time 1 or 2 machine cycles (10.8 or 21.6 μs), to instructions per second.
** Adding two 8-digit decimal numbers (32 bits each, assuming 4-bit BCD digits) takes a claimed 850 μs, or approximately 79 machine cycles (632 clock ticks), for an average of just under 10 cycles (80 ticks) per digit pair and an operating speed of 1176 × 8-digit additions per second
* Separate program and data storage. Contrary to Harvard architecture designs, however, which use separate buses, the 4004, with its need to keep pin count down, uses a single multiplexed 4-bit bus for transferring:
** 12-bit addresses,
** 8-bit instructions,
** 4-bit data words.
* Able to directly address 5120 bits (equivalent to 640 bytes) of RAM, stored as 1280 4-bit "characters" and organised into groups representing 1024 "data" and 256 "status" characters (512 and 128 bytes).
* Able to directly address bits of ROM, equivalent to and arranged as 4096 8-bit words (i.e. bytes).
* Instruction set contained 46 instructions (of which 41 were 8 bits wide and 5 were 16 bits wide).
* Register set contains 16 registers of 4 bits each.
* Internal subroutine stack, 3 levels deep.

Logic levels

Support chips

* 4001: 256-byte ROM (256 8-bit ''program'' instructions) and one built-in 4-bit I/O port. A 4001 ROM+I/O chip cannot be used in a system along with a 4008/4009 pair.
* 4002: 40-byte RAM (80 4-bit ''data'' words) and one built-in 4-bit output port; the RAM portion of the chip is organized into 4 "registers" of 20 4-bit words:
** 16 data words (used for mantissa digits in the original calculator design), accessed in a relatively standard manner,
** 4 status words (used for exponent digits and signs in the original calculator design), accessed using I/O type commands in place of the ROM's input channel.
* 4003: 10-bit parallel output shift register for scanning keyboards, displays, printers, etc.
* 4008: 8-bit address latch for access to standard memory chips and one built-in 4-bit chip-select and I/O port.
* 4009: program and I/O access converter to standard memory and I/O chips.
* 4269: keyboard/display interface.
* 4289: memory interface (combined functions of 4008 and 4009).

The minimum system specification described by Intel consists of a 4004 with a single 256-byte 4001 program ROM; there is no explicit need for separate RAM in minimal-complexity applications thanks to the 4004's large number of onboard index registers, which represent the equivalent of 16 × 4-bit or 8 × 8-bit characters (or a mixture) of working RAM, nor for simple interface chips thanks to the ROM's built-in I/O lines. However, as project complexity increases, the various other support chips start to become useful.

Packaging

Numerous versions of the Intel MCS-4 line of processors were produced. The earliest versions, marked C (like C4004), were ceramic and used a zebra pattern of white and gray on the back of the chips, often called "grey traces". The next generation of the chips was plain white ceramic (also marked C), and then dark grey ceramic (D). Many of the more recent versions of MCS-4 family were also produced with plastic (P).

File:Intel_C4004_b.jpg, The ceramic C4004 variant without grey traces
File:Intel_D4004.jpg, The ceramic D4004 variant
File:Intel_P4004.jpg, The plastic P4004 variant

Use

The first commercial product to use a microprocessor was the Busicom calculator 141-PF. The 4004 was also used in the first microprocessor-controlled pinball game, a prototype produced by Dave Nutting Associates for Bally in 1974.

In 1996, The US Patent Office officially recognized Mr. Gary W. Boone and his employer, Texas Instruments, as the inventors of the single-chip microcontroller, overturning the patent grant to Gilbert P. Hyatt in 1990. Even though the patent had expired, it was thought to have potential financial impact depending on the details of previous contracts with Gilbert Hyatt. According to Nick Tredennick, a microprocessor designer and expert witness to that Boone/Hyatt patent case:

A popular myth has it that Pioneer 10, the first spacecraft to leave the solar system, used an Intel 4004 microprocessor. According to Dr. Larry Lasher of Ames Research Center, the Pioneer team did evaluate the 4004, but decided it was too new at the time to include in any of the Pioneer projects. The myth was repeated by Federico Faggin himself in a lecture for the Computer History Museum in 2006.

Legacy and value

Federico Faggin signed the 4004 with his initials because he knew that his silicon gate design embodied "the essence of the microprocessor". A corner of the die reads "F.F."

On 15 November 2006, the 35th anniversary of the 4004, Intel celebrated by releasing the chip's schematics, mask works, and user manual.Intel 4004 Microprocessor Historical Materials
Intel Museum, 2009-11-15, accessed 2009-11-18 A fully functional 41 × 58 cm, 130× scale replica of the Intel 4004 was built using discrete transistors and put on display in 2006 at the Intel Museum in Santa Clara, California.

On 15 October 2010, Faggin, Hoff, and Mazor were awarded the National Medal of Technology and Innovation by President Barack Obama for their pioneering work on the 4004.

See also

* Central Air Data Computer - first 20-bit military microprocessor was released in June 1970 for US Navy F-14 Tomcat fighter jet, about 1.5 years before the Intel 4004 was released

Notes

References

Sources

Patents

* 14 August 1973. Faggin, Federico: Power supply settable bi-stable circuit.
* 28 June 1974. Hoff, Marcian; Mazor, Stanley; Faggin, Federico: Memory system for multi-chip digital computer.

Historical documents

Earliest documents on the MOS silicon gate technology for integrated circuits that enabled the 4004

*Faggin, F., Klein, T., and Vadasz, L.: Insulated Gate Field Effect Transistor Integrated Circuits with Silicon Gate
Cover and abstract of the IEDM (International Electron Devices Meeting) Program (October 1968)
The Silicon Gate Technology (SGT) was first presented by its developer, Federico Faggin, at the IEDM on 23 October 1968, in Washington, D.C. It was the only commercial process technology for the fabrication of MOS integrated circuits with self-aligned gate that was later universally adopted by the semiconductor industry. The SGT was the first technology to produce commercial dynamic RAMs, CCD image sensors, non volatile memories and the microprocessor, providing for the first time all the fundamental elements of a general purpose computer with LSI integrated circuits.
*Federico Faggin and Thomas Klein.: "A Faster Generation of MOS Devices with Low Thresholds is Riding the Crest of the New Wave, Silicon-Gate IC's
Cover of Electronics Magazine (29 September 1969)
The Electronics article introduces the Fairchild 3708, designed by Federico Faggin in 1968. It was the world's first commercial integrated circuit using the Silicon Gate Technology, proving its viability, and it was the first application of the new technology.
*F. Faggin, T. Klein: Silicon-Gate Technology. "Solid State Electronics", 1970, Vo. 13, pp. 1125–1144

Earliest documents on the Intel 4004

The 4004 bears the initials F.F. of its designer, Federico Faggin, etched on one corner of the chip. Signing the chip was a spontaneous gesture of proud authorship and was also an original idea imitated after him by many Intel designers.
*F. Faggin and M. E. Hoff: "Standard parts and custom design merge in four-chip processor kit". Electronics/24 April 1972, pp. 112–116. Reprinted on pp. 6–27 to 6–31 o
''The Intel Memory Design Handbook: August 1973''

*F. Faggin, M. Shima, M. E. Hoff Jr., H. Feeney, S. Mazor: "The MCS-4—An LSI micro computer system". IEEE '72 Region Six Conference. Reprinted on pp. 6–32 to 6–37 o
''The Intel Memory Design Handbook: August 1973''

Busicom 141-PF Printing Calculator Engineering Prototype (1971)
(Gift of Federico Faggin to the Computer History Museum, Mountain View, CA). The CHM collection catalog shows pictures of the engineering prototype of the Busicom 141-PF desktop calculator. The engineering prototype used the world's first microprocessor to have ever been produced. This one-of-a-kind prototype was a personal present by Busicom's president Mr. Yoshio Kojima to Federico Faggin for his successful leadership of the design and development of the 4004 and three other memory and I/O chips (the MCS-4 chipset). After keeping it in his home for 25 years, Faggin donated it to the CHM in 1996.
*Faggin, F.; Capocaccia, F. "A New Integrated MOS Shift Register", Proceedings XV International Electronics Scientific Congress, Rome, April 1968, pp. 143–152. This paper describes a novel static MOS shift register, developed at SGS-Fairchild (now ST Micro) at the end of 1967, before Federico Faggin joined Fairchild's R&D in Palo Alto (Ca) in February 1968. Faggin later used this new shift register in the MCS-4 chips, including the 4004(1970).

Further reading

*Faggin, Federico; Hoff, Marcian Jr.; Mazor, Stanley; Shima, Masatoshi (December 1996). "The history of the 4004". IEEE Micro. Vol. 16, no. 6. pp. 10–20.
Intel 4004 Microprocessor 35th Anniversary
- Live recording of presentations by Ted Hoff and Federico Faggin at the Computer History Museum for the 35th anniversary of the first microprocessor. (youtube.com)
*IEEE Solid State Circuits Magazine, Winter 2009 Vol.1 No.1
"The 4004 microprocessor of Faggin, Hoff, Mazor, and Shima".The MOS Silicon Gate Technology and the First Microprocessors
by Federico Faggin published in La Rivista del Nuovo Cimento, Italian Physical Society, Vol. 38, No. 12, 2015.
* "How we made the microprocessor" by Federico Faggin. Nature Electronics, Vol. 1, January 2018. Published online: 2018-01-08

External links

* ttp://www.intel4004.com/ The Intel 4004: A testimonial from Federico Faggin, designer of the 4004 and developer of its enabling technologybr>The New Methodology for Random Logic Design Used in the 4004 and in All the Early Intel MicroprocessorsInterview with Masatoshi ShimaIntel 4004 -- 45th Anniversary Project
Schematics at the unofficial 4004 website, and a simulator in Java. Fully functional 130x scale replicas of the 4004 built using discrete transistors.

* ttps://web.archive.org/web/20110723120701/http://www.flylogic.net/blog/?p=63 High resolution light microscope pictures of an Intel 4004 die together with a basic explanation of CMOS logicbr>Intel 4004 Emulator, Assembler, and Disassembler: Simple programming tools for Intel 4004 in JavascriptDatasheet Intel 4004Datasheet Intel MCS-4BuscomV2p1 schematicMSC-4 Assembly Language Programming ManualChip Hall of Fame: Intel 4004 Microprocessor
(IEEE Spectrum website)
Story of the Intel 4004

{{Intel processors, discontinued

4004
4-bit microprocessors