A digital timing diagram represents a set of signals in the time domain. A timing diagram can contain many rows, usually one of them being the clock. It is a tool commonly used in digital electronics, hardware debugging, and digital communications. Besides providing an overall description of the timing relationships, the digital timing diagram can help find and diagnose digital logic

hazards A hazard is a potential source of harm. Substances, events, or circumstances can constitute hazards when their nature would allow them, even just theoretically, to cause damage to health, life, property, or any other interest of value. The probabi ...

Diagram convention

Most timing diagrams use the following conventions: * Higher value is a logic one * Lower value is a logic zero * A slot showing a high and low is an either-or (such as on a data line) * A Z indicates

high impedance In electronics, high impedance means that a point in a circuit (a node) allows a relatively small amount of current through, per unit of applied voltage at that point. High impedance circuits are low current and potentially high voltage, whereas l ...

* A greyed out slot is a don't-care or indeterminate.

Example: SPI bus timing

The timing diagram example on the right describes the Serial Peripheral Interface (SPI) Bus. Most SPI master nodes can set the clock polarity (CPOL) and clock phase (CPHA) with respect to the data. This timing diagram shows the clock for both values of CPOL and the values for the two data lines (MISO & MOSI) for each value of CPHA. Note that when CPHA=1, then the data is delayed by one-half clock cycle. SPI operates in the following way: * The master determines an appropriate CPOL & CPHA value * The master pulls down the

slave select Chip select (CS) or slave select (SS) is the name of a control line in digital electronics used to select one (or a set) of integrated circuits (commonly called "chips") out of several connected to the same computer bus, usually utilizing the thr ...

(SS) line for a specific slave chip * The master clocks SCK at a specific frequency * During each of the eight clock cycles, the transfer is

full duplex A duplex communication system is a point-to-point system composed of two or more connected parties or devices that can communicate with one another in both directions. Duplex systems are employed in many communications networks, either to allow ...

: ** The master writes on the MOSI line and reads the MISO line ** The slave writes on the MISO line and reads the MOSI line * When finished the master can continue with another

byte The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of bits used to encode a single character of text in a computer and for this reason it is the smallest addressable uni ...

transfer or pull SS high to end the transfer When a slave's SS line is high, both its MISO and MOSI line should be high impedance to avoid disrupting a transfer to a different slave. Before SS being pulled low, the MISO & MOSI lines are indicated with a "z" for high impedance. Also, before the SS is pulled low, the "cycle #" row is meaningless and is shown greyed out. Note that for CPHA=1, the MISO & MOSI lines are undefined until after the first clock edge and are also shown greyed out before that. A more typical timing diagram has just a single clock and numerous data lines.

Software

The following diagram software may be used to draw timing diagrams: *

PlantUML PlantUML is an open-source tool allowing users to create diagrams from a plain text language. Besides various UML diagrams, PlantUML has support for various other software development related formats (such as Archimate, Block diagram, BPMN, C4, ...

External links

Wavedrom
is an online timing diagram editor.
Waves Editor
has a Windows binary. {{DEFAULTSORT:Digital Timing Diagram Diagrams Digital systems Logic Digital circuits