In computer architecture, cycles per instruction (aka clock cycles per instruction, clocks per instruction, or CPI) is one aspect of a processor's performance: the average number of clock cycles per instruction for a program or program fragment.[1] It is the multiplicative inverse of instructions per cycle. Contents 1 Definition 2 Explanation 3 Examples 3.1 Example 1 3.2 Example 2 4 See also 5 References Definition[edit] Cycles Per Instruction is defined by the following: C P I = Σ i ( I C i ) ( C C i ) I C displaystyle CPI= frac Sigma _ i (IC_ i )(CC_ i ) IC Where I C i displaystyle IC_ i is the number of instructions for a given instruction type i displaystyle i , C C i displaystyle CC_ i is the clock-cycles for that instruction type and I C = Σ i ( I C i ) displaystyle IC=Sigma _ i (IC_ i ) is the total instruction count. The summation sums over all instruction types for a given benchmarking process. Explanation[edit] Let us assume a classic RISC pipeline, with the following five stages: Instruction fetch cycle (IF). Instruction decode/Register fetch cycle (ID). Execution/Effective address cycle (EX). Memory access (MEM). Write-back cycle (WB). Each stage requires one clock cycle and an instruction passes through the stages sequentially. Without pipelining, a new instruction is fetched in stage 1 only after the previous instruction finishes at stage 5, therefore the number of clock cycles it takes to execute an instruction is five (CPI = 5 > 1). In this case, the processor is said to be subscalar. With pipelining, a new instruction is fetched every clock cycle by exploiting instruction-level parallelism, therefore, since one could theoretically have five instructions in the five pipeline stages at once (one instruction per stage), a different instruction would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1 (CPI = 1). In this case, the processor is said to be scalar. With a single-execution-unit processor, the best CPI attainable is 1. However, with a multiple-execution-unit processor, one may achieve even better CPI values (CPI < 1). In this case, the processor is said to be superscalar. To get better CPI values without pipelining, the number of execution units must be greater than the number of stages. For example, with six executions units, six new instructions are fetched in stage 1 only after the six previous instructions finish at stage 5, therefore on average the number of clock cycles it takes to execute an instruction is 5/6 (CPI = 5/6 < 1). To get better CPI values with pipelining, there must be at least two execution units. For example, with two executions units, two new instructions are fetched every clock cycle by exploiting instruction-level parallelism, therefore two different instructions would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1/2 (CPI = 1/2 < 1). Examples[edit] Example 1[edit] For the multi-cycle MIPS, there are five types of instructions: Load (5 cycles) Store (4 cycles) R-type (4 cycles) Branch (3 cycles) Jump (3 cycles) If a program has: 50% load instructions 15% R-type instructions 25% store instructions 8% branch instructions 2% jump instructions then, the CPI is: CPI = 5 × 50 + 4 × 15 + 4 × 25 + 3 × 8 + 3 × 2 100 = 4.4 displaystyle text CPI = frac 5times 50+4times 15+4times 25+3times 8+3times 2 100 =4.4 Example 2[edit]
[2] A 400-
Instruction TYPE
Instruction count
Integer Arithmetic 45000 1 Data transfer 32000 2 Floating point 15000 2 Control transfer 8000 2 Determine the effective CPI, MIPS (Millions of instructions per second)rate, and execution time for this program. CPI = 45000 × 1 + 32000 × 2 + 15000 × 2 + 8000 × 2 100000 = 155000 100000 = 1.55 displaystyle text CPI = frac 45000times 1+32000times 2+15000times 2+8000times 2 100000 = frac 155000 100000 =1.55 400 M h z = 400 , 000 , 000 H z displaystyle 400Mhz=400,000,000Hz since: M I P S ∝ 1 / C P I displaystyle MIPSpropto 1/CPI and M I P S ∝ c l o c k F r e q u e n c y displaystyle MIPSpropto clockFrequency Effective processor performance = MIPS = clock frequency CPI × 1 1 Million = 400 , 000 , 000 1.55 × 1000000 = 400 1.55 = 258 MIPS displaystyle text Effective processor performance = text MIPS = frac text clock frequency text CPI times frac 1 text 1 Million = frac 400,000,000 1.55times 1000000 = frac 400 1.55 =258, text MIPS Therefore: Execution time ( T ) = CPI × Instruction count × clock time = CPI × Instruction Count frequency = 1.55 × 100000 400 × 1000000 = 1.55 4000 = 0.0003875 sec = 0.3875 ms displaystyle text Execution time (T)= text CPI times text Instruction count times text clock time = frac text CPI times text Instruction Count text frequency = frac 1.55times 100000 400times 1000000 = frac 1.55 4000 =0.0003875, text sec =0.3875, text ms See also[edit] MIPS
References[edit] ^ Patterson, David A.; Hennessy, John L. Computer Organization and Design: The Hardware/Software Interface. ^ Advanced Computer Architecture by Kai Hwang, Chapter 1, Ex |