AVR32 is a

32-bit In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in a maximum of 32- bit units. Compared to smaller bit widths, 32-bit computers can perform la ...

RISC In electronics and computer science, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a comp ...

microcontroller architecture produced by Atmel. The microcontroller architecture was designed by a handful of people educated at the

Norwegian University of Science and Technology The Norwegian University of Science and Technology (NTNU; ) is a public university, public research university in Norway and the largest in terms of enrollment. The university's headquarters is located in Trondheim (city), Trondheim, with region ...

, including lead designer Øyvind Strøm and CPU architect Erik Renno in Atmel's Norwegian design center. Most instructions are executed in a single-cycle. The multiply–accumulate unit can perform a 32-bit × 16-bit + 48-bit arithmetic operation in two cycles (result latency), issued once per cycle. It does not resemble the 8-bit AVR microcontroller family, even though they were both designed at Atmel Norway, in

Trondheim Trondheim ( , , ; ), historically Kaupangen, Nidaros, and Trondhjem (), is a city and municipality in Trøndelag county, Norway. As of 2022, it had a population of 212,660. Trondheim is the third most populous municipality in Norway, and is ...

. Some of the debug-tools are similar. Support for AVR32 has been dropped from

Linux Linux ( ) is a family of open source Unix-like operating systems based on the Linux kernel, an kernel (operating system), operating system kernel first released on September 17, 1991, by Linus Torvalds. Linux is typically package manager, pac ...

as of kernel 4.12; Atmel has switched mostly to M variants of the

ARM architecture ARM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer, RISC instruction set architectures (ISAs) for central processing unit, com ...

Architecture

The AVR32 has at least two micro-architectures, the AVR32A and AVR32B. These differ in the instruction set architecture, register configurations and the use of caches for instructions and data. The AVR32A CPU cores are for inexpensive applications. They do not provide dedicated hardware registers for shadowing the register file, status and return address in

interrupt In digital computers, an interrupt (sometimes referred to as a trap) is a request for the processor to ''interrupt'' currently executing code (when permitted), so that the event can be processed in a timely manner. If the request is accepted ...

s. This saves chip area at the expense of slower interrupt-handling. The AVR32B CPU cores are designed for fast interrupts. They have dedicated registers to hold these values for interrupts, exceptions and supervisor calls. The AVR32B cores also support a

Java virtual machine A Java virtual machine (JVM) is a virtual machine that enables a computer to run Java programs as well as programs written in other languages that are also compiled to Java bytecode. The JVM is detailed by a specification that formally descr ...

in hardware. The AVR32 instruction set has

16-bit 16-bit microcomputers are microcomputers that use 16-bit microprocessors. A 16-bit register can store 216 different values. The range of integer values that can be stored in 16 bits depends on the integer representation used. With the two ...

(compact) and 32-bit (extended) instructions, similar to e.g. some ARM, with several specialized instructions not found in older ARMv5 or ARMv6 or

MIPS32 MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, ...

. Several U.S. patents are filed for the AVR32 ISA and design platform. Just like the AVR 8-bit microcontroller architecture, the AVR32 was designed for high

code density In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, ...

(packing much function in few instructions) and fast instructions with few clock cycles. Atmel used the independent benchmark consortium EEMBC to benchmark the architecture with various compilers and consistently outperformed both ARMv5 16-bit (

Thumb The thumb is the first digit of the hand, next to the index finger. When a person is standing in the medical anatomical position (where the palm is facing to the front), the thumb is the outermost digit. The Medical Latin English noun for thumb ...

) code and ARMv5 32-bit (

ARM In human anatomy, the arm refers to the upper limb in common usage, although academically the term specifically means the upper arm between the glenohumeral joint (shoulder joint) and the elbow joint. The distal part of the upper limb between ...

) code by as much as 50% on code-size and 3× on performance. Atmel says the "picoPower" AVR32 AT32UC3L consumes less than 0.48 mW/MHz in active mode, which it claimed, at the time, used less power than any other

CPU. Then in March 2015, Amtel claimed their new

Cortex-M0+ The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by ARM Limited. These cores are optimized for low-cost and energy-efficient integrated circuits, which have been embedded in tens of billions of consumer devices. Thoug ...

-based microcontrollers using

ARM Holdings Arm Holdings plc (formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a British semiconductor and software design company based in Cambridge, England, whose primary business is the design of central processing ...

, not their own

instruction set In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, s ...

, "has broken all ultra-low power performance barriers to date" by requiring only 35 μA/MHz.

Implementations

The AVR32 architecture was used only in Atmel's own products. In 2006, Atmel launched the AVR32A: The AVR32 AP7 core, a 7-stage pipelined,

cache Cache, caching, or caché may refer to: Science and technology * Cache (computing), a technique used in computer storage for easier data access * Cache (biology) or hoarding, a food storing behavior of animals * Cache (archaeology), artifacts p ...

-based design platform. This "AP7000" implements the AVR32B architecture, and supports a hardware FPU,

SIMD Single instruction, multiple data (SIMD) is a type of parallel computer, parallel processing in Flynn's taxonomy. SIMD describes computers with multiple processing elements that perform the same operation on multiple data points simultaneousl ...

(single instruction multiple data) DSP (

digital signal processing Digital signal processing (DSP) is the use of digital processing, such as by computers or more specialized digital signal processors, to perform a wide variety of signal processing operations. The digital signals processed in this manner are a ...

) instructions to the

instruction-set, in addition to Java hardware acceleration. It includes a Memory Management Unit (MMU) and supports operating systems like

. In early 2009, the rumored AP7200 follow-on processor was held back, with resources going into other chips. In 2007, Atmel launched the second AVR32: The AVR32 UC3 core. This is designed for microcontrollers, using on-chip flash memory for program storage and running without an MMU (memory management unit). The AVR32 UC3 core uses a three-stage pipelined Harvard architecture specially designed to optimize instruction fetches from on-chip

flash memory Flash memory is an Integrated circuit, electronic Non-volatile memory, non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for t ...

. The AVR32 UC3 core implements the AVR32A architecture. It shares the same instruction set architecture (ISA) as its AP7 sibling, but differs by not including the optional SIMD instructions or Java support. The FPU instruction set is optional, and was not implemented in the initial families of UC3 microcontrollers. It shares more than 220 instructions with the AVR32B. The ISA features atomic bit manipulation to control on-chip peripherals and general purpose I/Os and fixed point DSP arithmetic. Both implementations can be combined with a compatible set of peripheral controllers and buses first seen in the AT91SAM ARM-based platforms. Some peripherals first seen in the AP7000, such as the high speed USB peripheral controller, and standalone DMA controller, appeared later in updated ARM9 platforms and then in the ARM Cortex-M3 based products. Both AVR32 cores include a

Nexus NEXUS is a joint Canada Border Services Agency and U.S. Customs and Border Protection-operated Trusted Traveler and expedited border control program designed for pre-approved, low-risk travelers. Members of the program can avoid waits at border ...

class 2+ based On-Chip Debug framework build with

JTAG JTAG (named after the Joint Test Action Group which codified it) is an industry standard for verifying designs of and testing printed circuit boards after manufacture. JTAG implements standards for on-chip instrumentation in electronic design ...

. The UC3 C core, announced at the Electronica 2010 in Munich Germany on November 10, 2010, was the first member of the UC3 family to implement FPU support.

Devices

AP7 core

On April 10, 2012 Atmel announced the End of Life of AP7 Core devices from April 4, 2013.
AT32AP7000AT32AP7001AT32AP7002

UC3 core

If the devicename ends in *AU this is an Audio version, these allow the execution of Atmel licensed Audio firmware IPs. If the devicename ends in *S it includes an AES Crypto Module. ;A0/A1 Series ''devices deliver 91

Dhrystone Dhrystone is a synthetic computing benchmark program developed in 1984 by Reinhold P. Weicker intended to be representative of system (integer) programming. The Dhrystone grew to become representative of general processor ( CPU) performance. T ...

MIPS (DMIPS) at 66 MHz (1 flash wait-state) and consume 40 mA @66 MHz at 3.3 V.''
AT32UC3A0128

AT32UC3A0128AU

AT32UC3A0256

AT32UC3A0256AU

AT32UC3A0512

AT32UC3A0512AU

AT32UC3A1128

AT32UC3A1256AU

AT32UC3A1512

AT32UC3A1512AU
;A3/A4 Series ''devices deliver 91

MIPS (DMIPS) at 66 MHz and consume 40 mA @66 MHz at 3.3 V.''
AT32UC3A364

AT32UC3A364S

AT32UC3A3128

AT32UC3A3128S

AT32UC3A3256

AT32UC3A3256AU

AT32UC3A3256S

AT32UC3A464

AT32UC3A464S

AT32UC3A4128

AT32UC3A4128S

AT32UCA4256

AT32UC3A4256S
;B Series ''deliver 72 Dhrystone MIPS (DMIPS) at 60 MHz and consume 23 mA @66 MHz at 3.3V.''
AT32UC3B064

AT32UC3B0128

AT32UC3B0128AU

AT32UC3B0256

AT32UC3B0512

AT32UC3B0512AU

AT32UC3B164

AT32UC3B1128

AT32UC3B1256AT32UC3B1512
;C Series ''devices deliver 91

MIPS (DMIPS) at 66 MHz and consume 40 mA @66 MHz at 3.3 V.''
AT32UC3C064C

AT32UC3C0128C

AT32UC3C0256C

AT32UC3C0512C

AT32UC3C0512CAU

AT32UC3C164C

AT32UC3C1128C

AT32UC3C1256C

AT32UC3C1512C

AT32UC3C264C

AT32UC3C2128C

AT32UC3C2256C

AT32UC3C2512C
D Series ''The low-power UC3D embeds

SleepWalking Sleepwalking, also known as somnambulism or noctambulism, is a phenomenon of combined sleep and wakefulness. It is classified as a sleep disorder belonging to the parasomnia family. It occurs during the slow wave stage of sleep, in a state of ...

technology that allows a peripheral to wake the device from sleep mode.'' *
ATUC64D3
*
ATUC128D3
*
ATUC64D4
*
ATUC128D4
;L Series ''deliver 64 Dhrystone MIPS (DMIPS) at 50 MHz and consume 15 mA @50 MHz at 1.8 V.''
AT32UC3L016

AT32UC3L032

AT32UC3L064

AT32UC3L0128

AT32UC3L0256

ATUC64L3U

ATUC128L3U

ATUC256L3U

ATUC64L4U

ATUC128L4U

ATUC256L4U

Boards

AT32AP7000 development environment (STK1000)

AT32AP7000 Network Gateway Kit (NGW100)

AT32AP7000 board with FPGA, video decoder and Power over Ethernet (Hammerhead)

AT32AP7000 Indefia Embedded Linux Board with ZigBee support

All AT32UC3 Series Generic Evaluation platform (STK600)

AT32UC3A0/1 Series Evaluation Kit (EVK1100)

AT32UC3A0/1 Series Audio Evaluation Kit (EVK1105)

AT32UC3A3 Series Evaluation Kit (EVK1104)

AT32UC3B Series Evaluation Kit (EVK1101)

AT32UC3A1 Breakout/Small Development board (Aery32)

References

External links

Atmel AVR32
(now dead) contained recent Linux kernel patches and GCC /

binutils The GNU Binary Utilities, or , is a collection of programming tools maintained by the GNU Project for working with executable code including assembly, linking and many other development operations. The tools are originally from Cygnus Solut ...

and so on. {{RISC-based processor architectures Atmel microcontrollers Instruction set architectures