Phenom is the

64-bit In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit CPUs and ALUs are those that are based on processor registers, address buses, or data buses of that size. A ...

AMD desktop processor line based on the K10 microarchitecture, in what AMD calls family 10h (10 hex, i.e. 16 in normal decimal numbers) processors, sometimes incorrectly called "K10h". Triple-core versions (codenamed ''Toliman'') belong to the Phenom 8000 series and quad cores (codenamed ''Agena'') to the AMD Phenom X4 9000 series. The first processor in the family was released in 2007.

Background

AMD considers the quad core Phenoms to be the first "true" quad core design, as these processors are a monolithic multi-core design (all cores on the same silicon die), unlike Intel's

Core 2 Intel Core 2 is the processor family encompassing a range of Intel's consumer 64-bit x86-64 single-, dual-, and quad-core microprocessors based on the Core microarchitecture. The single- and dual-core models are single-die, whereas the quad-co ...

Quad series which are a

multi-chip module A multi-chip module (MCM) is generically an electronic assembly (such as a package with a number of conductor terminals or "pins") where multiple integrated circuits (ICs or "chips"), semiconductor dies and/or other discrete components are in ...

(MCM) design. The processors are on the Socket AM2+ platform. Before Phenom's original release a flaw was discovered in the

translation lookaside buffer A translation lookaside buffer (TLB) is a memory cache that stores the recent translations of virtual memory to physical memory. It is used to reduce the time taken to access a user memory location. It can be called an address-translation cache ...

(TLB) that could cause a system lock-up in rare circumstances; Phenom processors up to and including stepping "B2" and "BA" are affected by this bug. BIOS and software workarounds disable the TLB, and typically incur a performance penalty of at least 10%. This penalty was not accounted for in pre-release previews of Phenom, hence the performance of early Phenoms delivered to customers may have been less than the preview benchmarks. "B3" stepping Phenom processors were released March 27, 2008 without the TLB bug and with "xx50" model numbers. An AMD subsidiary released a patch for the

Linux kernel The Linux kernel is a free and open-source, monolithic, modular, multitasking, Unix-like operating system kernel. It was originally authored in 1991 by Linus Torvalds for his i386-based PC, and it was soon adopted as the kernel for the GNU ...

, to overcome this bug by software emulation of accessed- and dirty-bits. This method causes less performance loss than previous workarounds. The program was said in December 2007 to have received "minimal functional testing." AMD launched several models of the Phenom processor in 2007 and 2008 and an upgraded Phenom II in late 2008.

Features

CPU features table

Model naming methodology

The model numbers of the Phenom line of processors were changed from the PR system used in its predecessors, the

AMD Athlon 64 The Athlon 64 is a ninth-generation, AMD64-architecture microprocessor produced by Advanced Micro Devices (AMD), released on September 23, 2003. It is the third processor to bear the name ''Athlon'', and the immediate successor to the Athlon#Athlo ...

processor family. The Phenom model numbering scheme, for-later released Athlon X2 processors, is a four-digit model number whose first digit is a family indicator. Energy Efficient products end with an “e” suffix (for example, "Phenom 9350e"). Some Sempron processors use the prefix LE (for example, "Sempron LE-1200")

Cores

Phenom X4

''Agena'' (65 nm SOI)

* Four

AMD K10 The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. Though there were once reports that the K10 had been canceled,

cores * L1 cache: 64 KB + 64 KBIn this article, the conventional prefixes for computer memory denote base-2 values whereby “kilobyte” (KB) = 2¹⁰ bytes. (

data In the pursuit of knowledge, data (; ) is a collection of discrete values that convey information, describing quantity, quality, fact, statistics, other basic units of meaning, or simply sequences of symbols that may be further interpret ...

+ instructions) per core * L2 cache: 512 KB per core, full-speed * L3 cache: 2 MB shared among all cores * Memory controller: dual channel DDR2-1066 MHz with unganging option *

MMX MMX may refer to: * 2010, in Roman numerals Science and technology * MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel * MMX Mineração, a Brazilian mining company * Martian Moons eXploration, a Japane ...

, Extended

3DNow! 3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...

, SSE,

SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier SSE i ...

SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...

, SSE4a,

AMD64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...

, Cool'n'Quiet,

NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...

AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...

* Socket AM2+,

HyperTransport HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low- latency point-to-point link that was introduced on April 2 ...

with 1600 to 2000 MHz * Power consumption ( TDP): 65, 95, 125 and 140 Watt * First release ** November 19, 2007 (B2 Stepping) ** March 27, 2008 (B3 Stepping) * Clock rate: 1800 to 2600 MHz * Models: Phenom X4 9100e to 9950

Phenom X3

''Toliman'' (65 nm SOI)

* Three

AMD K10 The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. Though there were once reports that the K10 had been canceled,

cores chip harvested from Agena with one core disabled * L1 cache: 64 KB

and 64 KB instruction cache per core * L2 cache: 512 KB per core, full-speed * L3 cache: 2 MB shared between all cores * Memory controller: dual channel DDR2-1066 MHz with unganging option *