5 nanometer

In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the 5  nm process as the MOSFET technology node following the 7 nm node. In 2020, Samsung and TSMC entered volume production of 5 nm chips, manufactured for companies including Apple, Marvell, Huawei and Qualcomm.

The term "5 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 5 nm node is expected to have a contacted gate pitch of 51 nanometers and a tightest metal pitch of 30 nanometers. However, in real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption compared to the previous 7 nm process.

History

Background

Quantum tunnelling effects through the gate oxide layer on 7 nm and 5 nm transistors became increasingly difficult to manage using existing semiconductor processes. Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.

In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET.

In 2015, IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers.

In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the 5 nm node.

In 2017, IBM revealed that it had created 5 nm silicon chips, using silicon nanosheets in a '' gate-all-around'' configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm² and had 600 million transistors per mm², for a total of 30 billion transistors (1667 nm ² per transistor or 41 nm transistor spacing).

Commercialization

In April 2019, Samsung Electronics announced they had been offering their 5 nm process (5LPE) tools to their customers since 2018 Q4. In April 2019, TSMC announced that their 5 nm process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++. For the expected 28 nm minimum metal pitch, SALELE is the proposed best patterning method.

For their 5 nm process, Samsung started process defect mitigation by automated check and fix, due to occurrence of stochastic (random) defects in the metal and via layers.

In October 2019, TSMC reportedly started sampling 5 nm A14 processors for Apple.

In December 2019, TSMC announced an average yield of approximately 80%, with a peak yield per wafer of over 90% for their 5 nm test chips with a die size of 17.92 mm². In mid 2020 TSMC claimed its (N5) 5 nm process offered 1.8x the density of its 7 nm N7 process, with 15% speed improvement or 30% lower power consumption; an improved sub-version (N5P or N4) was claimed to improve on N5 with +5% speed or -10% power.

On October 13, 2020, Apple announced a new iPhone 12 lineup using the A14. Together with the Huawei Mate 40 lineup using the HiSilicon Kirin 9000, the A14 and Kirin 9000 were the first devices to be commercialized on TSMC's 5 nm node. Later, on November 10, 2020, Apple also revealed three new Mac models using the Apple M1, another 5 nm chip. According to Semianalysis, the A14 processor has a transistor density of 134 million transistors per mm².

In October 2021, TSMC introduced a new member of its 5 nm process family: N4P. Compared to N5, the node offers 11% higher performance (6% higher vs N4), 22% higher power efficiency, 6% higher transistor density and lower mask count. TSMC expects first tapeouts by the second half of 2022.

In December 2021, TSMC announced a new member of its 5 nm process family designed for HPC applications: N4X. The process features optimized transistor design and structures, reduced resistance and capacitance of targeted metal layers and high-density MiM capacitors. The process will offer up to 15% higher performance vs N5 (or up to 4% vs N4P) at 1.2 V and supply voltage in excess of 1.2 V. TSMC expects N4X to enter risk production by the first half of 2023.

In June 2022, Intel presented some details about the Intel 4 process: the company's first process to use EUV, 2x higher transistor density compared to Intel 7, use of cobalt-clad copper for the finest five layers of interconnect, 21.5% higher performance at iso power or 40% lower power at iso frequency at 0.65 V compared to Intel 7 etc. Intel's first product to be fabbed on Intel 4 is Meteor Lake, powered on in Q2 2022 and scheduled for shipping in 2023.

5 nm process nodes

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).

Beyond 5 nm

''3 nm'' (3-nanometer) is the usual term for the next node after 5 nm. , TSMC plans to commercialize the 3 nm node for 2022, while Samsung and Intel have plans for 2023.

3.5 nm has also been given as a name for the first node beyond 5 nm.

References

External links

5 nm lithography process

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Japanese inventions