3 nanometer

In semiconductor manufacturing, the 3 nm process is the next die shrink after the 5 nanometer MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. , Taiwanese chip manufacturer TSMC plans to put a 3 nm, semiconductor node termed N3 into volume production by the second half of 2022. An enhanced 3 nm chip process called N3e may start production in 2023. South Korean chipmaker Samsung officially targets the same time frame as TSMC (as of May 2022) with the start of 3 nm production in the first half of 2022 using 3GAE process technology and with 2nd-gen 3 nm process (named 3GAP) to follow in 2023, while according to other sources Samsung's 3 nm process will debut in 2024. American manufacturer Intel plans to start 3 nm production in 2023.

Samsung's 3 nm process is based on GAAFET (gate-all-around field-effect transistor) technology, a type of multi-gate MOSFET technology, while TSMC's 3 nm process will still use FinFET (fin field-effect transistor) technology, despite TSMC developing GAAFET transistors. Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (multi-bridge channel field-effect transistor). Intel's 3 nm process (dubbed "Intel 3" without the "nm" suffix) will use a refined, enhanced and optimized version of FinFET technology compared to its previous process nodes in terms of performance gained per watt, use of EUV lithography and power and area improvement.

The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers. However, in real world commercial practice, "3 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption. Moreover, there is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node. Typically the chip manufacturer refers to its own previous process node (in this case the 5 nm process node) for comparison. For example, TSMC has stated that its 3 nm FinFET chips will reduce power consumption by 25-30% at the same speed, increase speed by 10-15% at the same amount of power and increase transistor density by about 33% compared to its previous 5 nm FinFET chips. On the other hand, Samsung has stated that its 3 nm process will reduce power consumption by 45%, improve performance by 23%, and decrease surface area by 16% compared to its previous 5 nm process.

EUV faces new challenges at 3 nm which lead to the required use of multipatterning.

History

Research and technology demos

In 1985, a Nippon Telegraph and Telephone (NTT) research team fabricated a MOSFET ( NMOS) device with a channel length of 150 nm and gate oxide thickness of 2.5 nm. In 1998, an Advanced Micro Devices (AMD) research team fabricated a MOSFET (NMOS) device with a channel length of 50 nm and oxide thickness of 1.3 nm.

In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm, using the PMOS and NMOS processes. In 2006, a team from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center, developed a 3 nm width multi-gate MOSFET, the world's smallest nanoelectronic device, based on gate-all-around (GAAFET) technology.

Commercialization history

In late 2016, TSMC announced plans to construct a 5 nm–3 nm node semiconductor fabrication plant with a co-commitment investment of around US$15.7 billion.

In 2017, TSMC announced it was to begin construction of the 3 nm semiconductor fabrication plant at the Tainan Science Park in Taiwan. TSMC plans to start volume production of the 3 nm process node in 2023.

In early 2018, IMEC (Interuniversity Microelectronics Centre) and Cadence stated they had taped out 3 nm test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography.

In early 2019, Samsung presented plans to manufacture 3 nm GAAFET ( gate-all-around field-effect transistors) at the 3 nm node in 2021, using its own MBCFET transistor structure that uses nanosheets; delivering a 35% performance increase, 50% power reduction and a 45% reduction in area when compared with 7 nm. Samsung's semiconductor roadmap also included products at 8, 7, 6, 5, and 4 nm 'nodes'.

In December 2019, Intel announced plans for 3 nm production in 2025.

In January 2020, Samsung announced the production of the world's first 3 nm GAAFET process prototype, and said that it is targeting mass production in 2021.

In August 2020, TSMC announced details of its N3 3 nm process, which is new rather than being an improvement over its N5 5 nm process. Compared with the N5 process, the N3 process should offer a 10–15% (1.10–1.15×) increase in performance, or a 25–35% (1.25–1.35×) decrease in power consumption, with a 1.7× increase in logic density (a scaling factor of 0.58), a 20% increase (0.8 scaling factor) in SRAM cell density, and a 10% increase in analog circuitry density. Since many designs include considerably more SRAM than logic, (a common ratio being 70% SRAM to 30% logic) die shrinks are expected to only be of around 26%. TSMC plans volume production in the second half of 2022.

In July 2021, Intel presented brand new process technology roadmap, according to which Intel 3 process, the company's second node to use EUV and the last one to use FinFET before switching to Intel's RibbonFET transistor architecture, is now scheduled to enter product manufacturing phase in H2 2023.

In October 2021, Samsung adjusted earlier plans and announced that the company is scheduled to start producing its customers’ first 3 nm-based chip designs in the first half of 2022, while its second generation of 3 nm is expected in 2023.

In June 2022, at TSMC Technology Symposium, the company shared details of its N3E process technology scheduled for volume production in 2023 H2: 1.6× higher logic transistor density, 1.3× higher chip transistor density, 10-15% higher performance at iso power or 30-35% lower power at iso performance compared to TSMC N5 v1.0 process technology, FinFLEX technology, allowing to intermix libraries with different track heights within a block etc. TSMC also introduced new members of 3 nm process family: high-density variant N3S, high-performance variants N3P and N3X, and N3RF for RF applications.

In June 2022, Samsung started "initial" production of a low-power, high-performance chip using 3 nm process technology with GAA architecture. According to industry sources, Qualcomm has reserved some of 3 nm production capacity from Samsung.

On July 25, 2022, Samsung celebrated the first shipment of 3 nm Gate-All-Around chips to a Chinese cryptocurrency mining firm PanSemi. It was revealed that the newly introduced 3 nm MBCFET process technology offers 16% higher transistor density, 23% higher performance or 45% lower power draw compared to an unspecified 5 nm process technology. Goals for the second-generation 3 nm process technology include up to 35% higher transistor density, further reduction of power draw by up to 50% or higher performance by 30%.

3 nm process nodes

References

Further reading

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External links

3 nm lithography process

{{sequence
, prev = 5 nm (FinFET)
, list = MOSFET semiconductor device fabrication process
, next = 2 nm (GAAFET)

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