The 32 nm node is the step following the

45 nm process Per the International Technology Roadmap for Semiconductors, the 45 nm process is a MOSFET technology node referring to the average half-pitch of a memory cell manufactured at around the 2007–2008 time frame. Matsushita and Intel started mass ...

in CMOS ( MOSFET)

semiconductor device fabrication Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuit (IC) chips such as modern computer processors, microcontrollers, and memory chips such as NAND flash and DRAM that are p ...

. "32- nanometre" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technology level.

Toshiba , commonly known as Toshiba and stylized as TOSHIBA, is a Japanese multinational conglomerate corporation headquartered in Minato, Tokyo, Japan. Its diversified products and services include power, industrial and social infrastructure systems, ...

produced commercial 32

GiB The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of bits used to encode a single character of text in a computer and for this reason it is the smallest addressable unit ...

NAND flash Flash memory is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash, are named for the NOR and NAND logic gates. Both use ...

memory chips with the 32nm process in 2009.

Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the developers of the x86 seri ...

and

AMD Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufactur ...

produced commercial microchips using the 32-nanometre process in the early 2010s. IBM and the

Common Platform Common may refer to: Places * Common, a townland in County Tyrone, Northern Ireland * Boston Common, a central public park in Boston, Massachusetts * Cambridge Common, common land area in Cambridge, Massachusetts * Clapham Common, originally com ...

also developed a 32 nm high-κ metal gate process. Intel began selling its first 32 nm processors using the Westmere architecture on 7 January 2010. The 28-nanometre node was an intermediate half-node

die shrink The term die shrink (sometimes optical shrink or process shrink) refers to the scaling of metal-oxide-semiconductor (MOS) devices. The act of shrinking a die is to create a somewhat identical circuit using a more advanced fabrication process, ...

based on the 32-nanometre process. The 32 nm process was superseded by commercial

22 nm The 22 nm node is the process step following 32 nm in CMOS MOSFET semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm. ...

technology in 2012."Report: Intel Scheduling 22 nm Ivy Bridge for April 2012"
Tom'sHardware.com. 26 November 2011. Retrieved 5 December 2011.

Technology demos

Prototypes using 32 nm technology first emerged in the mid-2000s, following the development of pitch

double patterning Multiple patterning (or multi-patterning) is a class of technologies for manufacturing integrated circuits (ICs), developed for photolithography to enhance the feature density. It is expected to be necessary for the 10 nm and 7 nm node se ...

by Gurtej Singh Sandhu at Micron Technology, which led to the development of

memory below 40nm. In 2004, IBM demonstrated a 0.143 μm² SRAM cell with a poly gate pitch of 135 nm, produced using

electron-beam lithography Electron-beam lithography (often abbreviated as e-beam lithography, EBL) is the practice of scanning a focused beam of electrons to draw custom shapes on a surface covered with an electron-sensitive film called a resist (exposing). The electron b ...

and photolithography on the same layer. It was observed that the cell's sensitivity to input voltage fluctuations degraded significantly at such a small scale. In October 2006, the

Interuniversity Microelectronics Centre Interuniversity Microelectronics Centre (IMEC) is an international research & development organization, active in the fields of nanoelectronics and digital technologies, with headquarters in Belgium. Luc Van den hove has served as President and ...

(IMEC) demonstrated a 32 nm flash patterning capability based on

and immersion lithography. The necessity of introducing double patterning and hyper-NA tools to reduce memory cell area offset some of the cost advantages of moving to this node from the 45 nm node.

TSMC Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational semiconductor contract manufacturing and design company. It is the world's most valuable semiconductor company, the world' ...

similarly used double patterning combined with immersion lithography to produce a 32 nm node 0.183 μm² six-transistor SRAM cell in 2005. Intel Corporation revealed its first 32 nm test chips to the public on 18 September 2007 at the Intel Developer Forum. The test chips had a cell size of 0.182 μm², used a second-generation high-κ gate dielectric and metal gate, and contained almost two billion transistors. 193 nm immersion lithography was used for the critical layers, while 193 nm or 248 nm dry lithography was used on less critical layers. The critical pitch was 112.5 nm. In January 2011, Samsung completed development of the industry's first

DDR4 Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth (" double data rate") interface. Released to the market in 2014, it is a variant of dynamic ra ...

SDRAM module using a process technology with a size between 30 nm and 39 nm. The module could reportedly achieve data transfer rates of 2.133 Gbit/s at 1.2V, compared to 1.35V and 1.5V DDR3 DRAM at an equivalent 30 nm-class process technology with speeds of up to 1.6 Gbit/s. The module used pseudo open drain (POD) technology, specially adapted to allow DDR4 SDRAM to consume just half the current of

DDR3 Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth (" double data rate") interface, and has been in use since 2007. It is the higher-spee ...

when reading and writing data.

Processors using 32 nm technology

Intel's Core i3 and i5 processors, released in January 2010, were among the first mass-produced processors to use 32 nm technology. Intel's second-generation Core processors, codenamed

Sandy Bridge Sandy Bridge is the codename for Intel's 32 nm microarchitecture used in the second generation of the Intel Core processors (Core i7, i5, i3). The Sandy Bridge microarchitecture is the successor to Nehalem and Westmere microarchitecture. ...

, also used the 32 nm manufacturing process. Intel's 6-core processor, codenamed

Gulftown Gulftown or Westmere-EP is the codename of an up to six-core hyperthreaded Intel processor able to run up to 12 threads in parallel. It is based on Westmere microarchitecture, the 32 nm shrink of Nehalem. Originally rumored to be called the Int ...

and built on the Westmere architecture, was released on 16 March 2010 as the Core i7 980x Extreme Edition, retailing for approximately US$1,000. Intel's lower-end 6-core, the i7-970, was released in late July 2010, priced at approximately US$900. AMD also released 32 nm SOI processors in the early 2010s. AMD's FX Series processors, codenamed Zambezi and based on AMD's Bulldozer architecture, were released in October 2011. The technology utilised a 32 nm SOI process, two CPU cores per module, and up to four modules, ranging from a quad-core design costing approximately US$130 to a $280 eight-core design. In September 2011, Ambarella Inc. announced the availability of the 32 nm-based A7L

system-on-a-chip A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memory ...

circuit for digital still cameras, providing

1080p60 1080p (1920×1080 progressively displayed pixels; also known as Full HD or FHD, and BT.709) is a set of HDTV high-definition video modes characterized by 1,920 pixels displayed across the screen horizontally and 1,080 pixels down the screen verti ...

high-definition video capabilities.

Successor node

28 nm & 22 nm

The successor to 32 nm technology was the 22 nm node, per the

International Technology Roadmap for Semiconductors The International Technology Roadmap for Semiconductors (ITRS) is a set of documents produced by a group of semiconductor industry experts. These experts are representative of the sponsoring organisations which include the Semiconductor Industry A ...

. Intel began mass production of 22 nm semiconductors in late 2011, and announced the release of its first commercial 22 nm devices in April 2012.

bypassed 32nm, jumping from 40nm in 2008 to 28nm in 2011.

References

External links