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In computer architecture, 12 8-bit integers, memory addresses, or other data units are those that are 128 bits (16 octets) wide. Also, 12 8-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. While there are currently no mainstream general-purpose processors built to operate on 12 8-bit integers or addresses, a number of processors do have specialized ways to operate on 12 8-bit chunks of data. The IBM System/370
IBM System/370
could be considered the first simple 128-bit computer, as it used 12 8-bit floating-point registers. Most modern CPUs feature single-instruction multiple-data (SIMD) instruction sets (Streaming SIMD
SIMD
Extensions, AltiVec etc.) where 12 8-bit vector registers are used to store several smaller numbers, such as four 32-bit
32-bit
floating-point numbers. A single instruction can then operate on all these values in parallel. However, these processors do not operate on individual numbers that are 128 binary digits in length; only their registers have the size of 128 bits. The DEC VAX
VAX
supported operations on 12 8-bit integer ('O' or octaword) and 12 8-bit floating-point ('H-float' or HFLOAT) datatypes. Support for such operations was an upgrade option rather than being a standard feature. Since the VAX's registers were 32 bits wide, a 128-bit operation used four consecutive registers or four longwords in memory. The ICL 2900 Series
ICL 2900 Series
provided a 12 8-bit accumulator, and its instruction set included 12 8-bit floating-point and packed decimal arithmetic. In the same way that compilers emulate e.g. 6 4-bit
4-bit
integer arithmetic on architectures with register sizes less than 64 bits, some compilers also support 12 8-bit integer arithmetic. For example, the GCC C compiler 4.6 and later has a 12 8-bit integer type __int128 for some architectures.[1] For the C programming language, this is a compiler-specific extension, as C11 itself does not guarantee support for 12 8-bit integers. A 12 8-bit register can store 2128 (over 3.40 × 1038) different values. The range of integer values that can be stored in 128 bits depends on the integer representation used. With the two most common representations, the range is 0 through 340,282,366,920,938,463,463,374,607,431,768,211,455 (2128 − 1) for representation as an (unsigned) binary number, and −170,141,183,460,469,231,731,687,303,715,884,105,728 (−2127) through 170,141,183,460,469,231,731,687,303,715,884,105,727 (2127 − 1) for representation as two's complement. Uses[edit]

The free software used to implement RISC-V
RISC-V
architecture is defined for 32, 64 and 128 bits of integer data width. Universally Unique Identifiers (UUID) consist of a 12 8-bit value. IPv6
IPv6
routes computer network traffic amongst a 12 8-bit range of addresses. ZFS
ZFS
is a 12 8-bit file system. GPU
GPU
chips commonly move data across a 12 8-bit bus.[2] 128 bits is a common key size for symmetric ciphers and a common block size for block ciphers in cryptography. 12 8-bit processors could be used for addressing directly up to 2128 (over 3.40 × 1038) bytes, which would greatly exceed the total data stored on Earth as of 2010, which has been estimated to be around 1.2 zettabytes (1.42 × 1021 bytes).[3] Quadruple precision
Quadruple precision
(128-bit) floating-point numbers can store 64-bit fixed point numbers or integers accurately without losing precision. The AS/400
AS/400
virtual instruction set defines all pointers as 128-bit. This gets translated to the hardware's real instruction set as required, allowing the underlying hardware to change without needing to recompile the software. Past hardware was 4 8-bit CISC, while current hardware is 6 4-bit
4-bit
PowerPC. Because pointers are defined to be 128-bit, future hardware may be 12 8-bit without software incompatibility. Increasing the word size can speed up multiple precision mathematical libraries. Applications include cryptography, and potentially speed up algorithms used in complex mathematical processing (numerical analysis, signal processing, complex photo editing and audio and video processing). MD5
MD5
algorithm is a widely used hash function producing a 12 8-bit hash value.

History[edit] A 12 8-bit multicomparator was described by researchers in 1976.[4] A CPU with 12 8-bit multimedia extensions was designed by researchers in 1999.[5] References[edit]

^ "GCC 4.6 Release Series - Changes, New Features, and Fixes". Retrieved 25 July 2016.  ^ Don Woligroski (July 2006). "The Graphics Processor". tomshardware.com. Retrieved 24 February 2013.  ^ Rich Miller (May 2010). "Digital Universe nears a Zettabyte". The Guardian. datacenterknowledge.com. Retrieved 16 September 2010.  ^ Mead, C.A.; Pashley, R.D.; Britton, L.D.; Daimon, Y.T.; Sando, S.F. (1976). "12 8-bit multicomparator". IEEE Journal of Solid-State Circuits. 11: 692. doi:10.1109/JSSC.1976.1050799.  ^ Suzuoki, M.; Kutaragi, K.; Hiroi, T.; Magoshi, H.; Okamoto, S.; Oka, M.; Ohba, A.; Yamamoto, Y.; Furuhashi, M.; Tanaka, M.; Yutaka, T.; Okada, T.; Nagamatsu, M.; Urakawa, Y.; Funyu, M.; Kunimatsu, A.; Goto, H.; Hashimoto, K.; Ide, N.; Murakami, H.; Ohtaguro, Y.; Aono, A. (1999). "A microprocessor with a 12 8-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder". IEEE Journal of Solid-State Circuits. 34 (11): 1608. doi:10.1109/4.799870. 

v t e

CPU technologies

Architecture

Turing machine Post–Turing machine Universal Turing machine Quantum Turing machine Belt machine Stack machine Register machine Counter machine Pointer machine Random access machine Random access stored program machine Finite-state machine Queue automaton Von Neumann Harvard (modified) Dataflow TTA Cellular Artificial neural network

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Asymmetric multiprocessing
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Itanium
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Word size

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Execution

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Bubble Operand forwarding

Out-of-order execution

Register renaming

Speculative execution

Branch predictor Memory dependence prediction

Hazards

Parallel level

Bit

Bit-serial Word

Instruction Pipelining

Scalar Superscalar

Task

Thread Process

Data

Vector

Memory

Multithreading

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Flynn's taxonomy

SISD SIMD
SIMD
(SWAR) SIMT MISD MIMD

SPMD

Addressing mode

CPU performance

Instructions per second (IPS) Instructions per clock (IPC) Cycles per instruction (CPI) Floating-point
Floating-point
operations per second (FLOPS) Transactions per second (TPS) Synaptic Updates Per Second (SUPS) Performance per watt Orders of magnitude (computing) Cache performance measurement and metric

Core count

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Types

Central processing unit
Central processing unit
(CPU) GPGPU AI accelerator Vision processing unit (VPU) Vector processor Barrel processor Stream processor Digital signal processor
Digital signal processor
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Physics processing unit
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Multi-chip module
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System on a chip
(SoC) Multiprocessor system-on-chip (MPSoC) Programmable System-on-Chip
System-on-Chip
(PSoC) Network on a chip (NoC)

Components

Execution unit (EU) Arithmetic logic unit
Arithmetic logic unit
(ALU) Address generation unit
Address generation unit
(AGU) Floating-point
Floating-point
unit (FPU) Load-store unit (LSU) Branch predictor Unified Reservation Station Barrel shifter Uncore Sum addressed decoder (SAD) Front-side bus Back-side bus Northbridge (computing) Southbridge (computing) Adder (electronics) Binary multiplier Binary decoder Address decoder Multiplexer Demultiplexer Registers Cache Memory management unit
Memory management unit
(MMU) Input–output memory management unit
Input–output memory management unit
(IOMMU) Integrated Memory Controller (IMC) Power Management Unit (PMU) Translation lookaside buffer
Translation lookaside buffer
(TLB) Stack engine Register file Processor register Hardware register Memory buffer register (MBR) Program counter Microcode
Microcode
ROM Datapath Control unit Instruction unit Re-order buffer Data buffer Write buffer Coprocessor Electronic switch Electronic circuit Integrated circuit Three-dimensional integrated circuit Boolean circuit Digital circuit Analog circuit Mixed-signal integrated circuit Power management integrated circuit Quantum circuit Logic gate

Combinational logic Sequential logic Emitter-coupled logic
Emitter-coupled logic
(ECL) Transistor–transistor logic
Transistor–transistor logic
(TTL) Glue logic

Quantum gate Gate array Counter (digital) Bus (computing) Semiconductor device Clock rate CPU multiplier Vision chip Memristor

Power management

APM ACPI Dynamic frequency scaling Dynamic voltage scaling Clock gating

Hardware security

Non-executable memory (NX bit) Memory Protection Extensions (Intel MPX) Intel Secure Key Hardware restriction (firmware) Software Guard Extensions (Intel SGX) Trusted Execution Technology Trusted Platform Module
Trusted Platform Module
(TPM) Secure cryptoprocessor Hardware security module Hengzhi chip

Related

History of ge

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