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LGA 2066
LGA 2066, also called Socket R4, is a CPU socket
CPU socket
by Intel
Intel
that debuted with Skylake-X and Kaby Lake-X processors in June 2017. It replaces Intel's LGA 2011 -3 (R3) in the performance, high-end desktop and Workstation platforms (based on the X299 "Basin Falls" and C422 chipsets), while LGA 3647 (Socket P) will replace LGA 2011-3 (R3) in the server platforms based on Skylake-SP ( Xeon
Xeon
"Purley"). CONTENTS* 1 Compatible processors * 1.1 Desktop (Skylake-X/Kaby Lake-X) * 1.2 Workstation (Skylake-SP) * 2 References COMPATIBLE PROCESSORSDESKTOP (SKYLAKE-X/KABY LAKE-X)Desktop processors for the LGA 2066
LGA 2066
socket are listed in the table below
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Intel
Coordinates : 37°23′16.54″N 121°57′48.74″W / 37.3879278°N 121.9635389°W / 37.3879278; -121.9635389 Intel
Intel
Corporation Intel
Intel
Corporation's current logo, used since 2006 Intel's headquarters in Santa Clara , California
California
FORMERLY CALLED N M Electronics
Electronics
(1968) TYPE Public TRADED AS * NASDAQ
NASDAQ
: INTC * NASDAQ-100 Component * DJIA Component * S&P 100 Component * S 49 years ago (1968-07-18) FOUNDERS Gordon Moore
Gordon Moore
Robert Noyce HEADQUARTERS Santa Clara , California
California
, U.S
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Turbo Boost
INTEL TURBO BOOST is Intel
Intel
's trade name for a feature that automatically raises certain of its processors ' operating frequency , and thus performance, when demanding tasks are running. Turbo-Boost-enabled processors are the Core i5 and Core i7 series manufactured since 2008, more particularly, those based on the Nehalem , Sandy Bridge , and later microarchitectures . The frequency is accelerated when the operating system requests the highest performance state of the processor. Processor performance states are defined by the Advanced Configuration and Power Interface (ACPI) specification, an open standard supported by all major operating systems; no additional software or drivers are required to support the technology. The design concept behind Turbo Boost is commonly referred to as "dynamic overclocking "
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Socket 2
SOCKET 2 was one of the series of CPU sockets into which various x86 microprocessors were inserted. It was an updated Socket 1 with added support for Pentium OverDrive processors. Socket 2
Socket 2
was a 238-pin low insertion force (LIF) or zero insertion force (ZIF) 19×19 pin grid array (PGA) socket suitable for the 5-volt , 25 to 50 MHz
MHz
486 SX , 486 DX , 486 DX2 , 486 OverDrive and 63 or 83 MHz
MHz
Pentium OverDrive processors
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Pentium II
The PENTIUM II brand refers to Intel
Intel
's sixth-generation microarchitecture ("P6 ") and x86 -compatible microprocessors introduced on May 7, 1997. Containing 7.5 million transistors (27.4 million in the case of the mobile Dixon with 256 KB L2 cache ), the Pentium II featured an improved version of the first P6-generation core of the Pentium Pro , which contained 5.5 million transistors. However, its L2 cache subsystem was a downgrade when compared to Pentium Pros. In early 1999, the Pentium II was superseded by the almost identical Pentium III , which basically only added SSE instructions to the CPU
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Pin Grid Array
A PIN GRID ARRAY, often abbreviated PGA, is a type of integrated circuit packaging . In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart, and may or may not cover the entire underside of the package. PGAs are often mounted on printed circuit boards using the through hole method or inserted into a socket . PGAs allow for more pins per integrated circuit than older packages such as dual in-line package (DIP)
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Xeon
The XEON /ˈziːɒn/ is a brand of x86 microprocessors designed, manufactured, and marketed by Intel
Intel
, targeted at the non-consumer workstation , server , and embedded system markets. The primary advantages of the Xeon
Xeon
CPUs , when compared to the majority of Intel's desktop-grade consumer CPUs, are their multi-socket capabilities, higher core counts, larger cache memory , and support for ECC memory . A Xeon Phi co-processor, or co-processors, can be used alongside an existing Intel
Intel
Xeon
Xeon
processor to provide increased/improved computing power, requiring an available PCI Express 3.0 ×16 slot in ×16, or ×8 mode
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Intel Itanium
ITANIUM (/aɪˈteɪniəm/ eye-TAY-nee-əm ) is a family of 64-bit Intel
Intel
microprocessors that implement the Intel
Intel
Itanium architecture (formerly called IA-64). Intel
Intel
markets the processors for enterprise servers and high-performance computing systems. The Itanium architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and Intel. Itanium-based systems have been produced by HP (the HP Integrity Servers line) and several other manufacturers. In 2008, Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems , behind x86-64 , Power Architecture , and SPARC
SPARC

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Socket 3
SOCKET 3 was a series of CPU Sockets for various x86 microprocessors . It was sometimes found alongside a secondary socket designed for a math coprocessor chip, in this case the 487 . Socket 3
Socket 3
resulted from Intel's creation of lower voltage microprocessors. An upgrade to Socket 2
Socket 2
, it rearranged the pin layout and omitted one pin so that 3.3 V processors could not be plugged into older 5 V only sockets
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Edge Connector
An EDGE CONNECTOR is the portion of a printed circuit board (PCB) consisting of traces leading to the edge of the board that are intended to plug into a matching socket . The edge connector is a money-saving device because it only requires a single discrete female connector (the male connector is formed out of the edge of the PCB), and they also tend to be fairly robust and durable. They are commonly used in computers for expansion slots for peripheral cards, such as PCI , PCI Express , and AGP cards. CONTENTS * 1 Socket design * 2 Uses * 3 See also * 4 References SOCKET DESIGN Edge connector
Edge connector
sockets consist of a plastic "box" open on one side, with pins on one or both side(s) of the longer edges, sprung to push into the middle of the open center. Connectors are often keyed to ensure the correct polarity , and may contain bumps or notches both for polarity and to ensure that the wrong type of device is not inserted
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Flip Chip
FLIP CHIP, also known as CONTROLLED COLLAPSE CHIP CONNECTION or its abbreviation, C4, is a method for interconnecting semiconductor devices , such as IC chips and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads. The technique was developed by General Electric
General Electric
's Light Military Electronics Dept., Utica, N.Y. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry (e.g., a circuit board or another chip or wafer), it is flipped over so that its top side faces down, and aligned so that its pads align with matching pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding , in which the chip is mounted upright and wires are used to interconnect the chip pads to external circuitry
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Intel Corporation
Coordinates : 37°23′16.54″N 121°57′48.74″W / 37.3879278°N 121.9635389°W / 37.3879278; -121.9635389 Intel
Intel
Corporation Intel's current logo, used since 2006 Intel's headquarters in Santa Clara , California
California
TYPE Public TRADED AS * NASDAQ
NASDAQ
: INTC * NASDAQ-100 Component * DJIA Component * S&P 100 Component * S 49 years ago (1968-07-18) FOUNDERS Gordon Moore
Gordon Moore
Robert Noyce
Robert Noyce
HEADQUARTERS Santa Clara, California
Santa Clara, California
, U.S
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Intel QuickPath Interconnect
The INTEL QUICKPATH INTERCONNECT (QPI) is a point-to-point processor interconnect developed by Intel
Intel
which replaced the front-side bus (FSB) in Xeon
Xeon
, Itanium
Itanium
, and certain desktop platforms starting in 2008. Prior to the name's announcement, Intel
Intel
referred to it as COMMON SYSTEM INTERFACE (CSI). Earlier incarnations were known as Yet Another Protocol (YAP) and YAP+. QPI 1.1 is a significantly revamped version introduced with Sandy Bridge-EP ( Romley platform). QPI will be replaced by Intel
Intel
UltraPath Interconnect (UPI) in future Skylake EX/EP Xeon
Xeon
processors based on LGA 3647 socket
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Front-side Bus
A FRONT-SIDE BUS (FSB) was a computer communication interface (bus ) often used in Intel
Intel
-chip-based computers during the 1990s and 2000s. The competing EV6 bus served the same function for AMD
AMD
CPUs. Both typically carry data between the central processing unit (CPU) and a memory controller hub, known as the northbridge . Depending on the implementation, some computers may also have a back-side bus that connects the CPU to the cache . This bus and the cache connected to it are faster than accessing the system memory (or RAM) via the front-side bus. The speed of the front side bus is often used as an important measure of the performance of a computer. The original front-side bus architecture has been replaced by HyperTransport
HyperTransport
, Intel
Intel
QuickPath Interconnect or Direct Media Interface in modern volume CPUs
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Socket 4
SOCKET 4, presented in 1993, was the first CPU socket
CPU socket
designed for the early P5 Pentium microprocessors . Socket 4
Socket 4
was the only 5-volt socket for the Pentium. After Socket 4, Intel
Intel
switched to the 3.3-volt-powered Socket 5
Socket 5
. Socket 4
Socket 4
does support a special Pentium OverDrive , which allows running at 120 MHz (for the 60 MHz Pentium) or 133 MHz (for the 66 MHz Pentium)
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