A wide-issue architecture is a computer processor that issues more than one
instruction per clock cycle. They can be considered in three broad types:
* Statically-scheduled
superscalar
A superscalar processor (or multiple-issue processor) is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single in ...
architectures execute instructions in the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle.
*
VLIW
Very long instruction word (VLIW) refers to instruction set architectures that are designed to exploit instruction-level parallelism (ILP). A VLIW processor allows programs to explicitly specify instructions to execute in parallel computing, para ...
architectures rely on the programming software (compiler) to determine which instructions to dispatch on a given clock cycle.
* Dynamically-scheduled superscalar architectures execute instructions in an order that gives the same result as the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle.
See also
*
Out-of-order execution
In computer engineering, out-of-order execution (or more formally dynamic execution) is an instruction scheduling paradigm used in high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In t ...
*
Explicitly parallel instruction computing
Explicitly parallel instruction computing (EPIC) is a term coined in 1997 by the Itanium, HP–Intel alliance to describe a computing paradigm that researchers had been investigating since the early 1980s. This paradigm is also called ''Independe ...
References
Instruction processing
Parallel computing
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