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The subthreshold slope is a feature of a
MOSFET upright=1.3, Two power MOSFETs in amperes">A in the ''on'' state, dissipating up to about 100 watt">W and controlling a load of over 2000 W. A matchstick is pictured for scale. In electronics, the metal–oxide–semiconductor field- ...
's current–voltage characteristic. In the subthreshold region, the drain current behaviour—though being controlled by the
gate A gate or gateway is a point of entry to or from a space enclosed by walls. The word is derived from Proto-Germanic language, Proto-Germanic ''*gatan'', meaning an opening or passageway. Synonyms include yett (which comes from the same root w ...
terminal—is similar to the exponentially decreasing current of a forward biased diode. Therefore, a plot of drain current versus gate voltage with drain, source, and bulk voltages fixed will exhibit approximately log-linear behaviour in this MOSFET operating regime. Its slope is the subthreshold slope. The subthreshold slope is also the reciprocal value of the subthreshold swing ''Ss-th'' which is usually given as:''Physics of Semiconductor Devices'', S. M. Sze. New York: Wiley, 3rd ed., with Kwok K. Ng, 2007, chapter 6.2.4, p. 315, . S_ = \ln(10) \left(1+\right) C_d = depletion layer capacitance C_ = gate-oxide capacitance = thermal voltage The minimum subthreshold swing of a conventional device can be found by letting \textstyle \rightarrow 0 and/or \textstyle \rightarrow \infty , which yield S_ = \ln(10) (known as thermionic limit) and 60 mV/dec at room temperature (300 K). A typical experimental subthreshold swing for a scaled MOSFET at room temperature is ~70 mV/dec, slightly degraded due to short-channel MOSFET parasitics. A ''dec'' (decade) corresponds to a 10 times increase of the drain current ''ID''. A device characterized by steep subthreshold slope exhibits a faster transition between off (low current) and on (high current) states.


References


External links


Optimization of Ultra-Low-Power CMOS Transistors
Michael Stockinger, 2000 {{DEFAULTSORT:Subthreshold Slope Transistor modeling