A single cycle processor is a processor that carries out one instruction in a single
clock cycle.
See also
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Complex instruction set computer, a processor executing one instruction in multiple clock cycles
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DLX
The DLX (pronounced "Deluxe") is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the Stanford MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC desi ...
, a very similar architecture designed by
John L. Hennessy (creator of MIPS) for teaching purposes
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MIPS architecture
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, ...
, MIPS-32 architecture
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MIPS-X, developed as a follow-on project to the MIPS architecture
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Reduced instruction set computer
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set compu ...
, a processor executing one instruction in minimal clock cycles
References
External links
Microprocessors
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