Power ISA is a

reduced instruction set computer In electronics and computer science, a reduced instruction set computer (RISC) is a computer architecture designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a com ...

(RISC)

instruction set architecture In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, ...

(ISA) currently developed by the

OpenPOWER Foundation The OpenPOWER Foundation is a collaboration around Power ISA-based products initiated by IBM and announced as the "OpenPOWER Consortium" on August 6, 2013. IBM's focus is to open up technology surrounding their Power Architecture offerings, such ...

, led by

IBM International Business Machines Corporation (using the trademark IBM), nicknamed Big Blue, is an American Multinational corporation, multinational technology company headquartered in Armonk, New York, and present in over 175 countries. It is ...

. It was originally developed by IBM and the now-defunct Power.org industry group. Power ISA is an evolution of the

PowerPC PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple Inc., App ...

ISA, created by the mergers of the core PowerPC ISA and the optional Book E for embedded applications. The merger of these two components in 2006 was led by Power.org founders IBM and

Freescale Semiconductor Freescale Semiconductor, Inc. was an American semiconductor manufacturer. It was created by the divestiture of the Semiconductor Products Sector of Motorola in 2004. Freescale focused their integrated circuit products on the automotive, embedde ...

. Prior to version 3.0, the ISA is divided into several categories. Processors implement a set of these categories as required for their task. Different classes of processors are required to implement certain categories, for example a server-class processor includes the categories: ''Base'', ''Server'', ''Floating-Point'', ''64-Bit'', etc. All processors implement the Base category. Power ISA is a RISC load/store architecture. It has multiple sets of registers: * ''32'' × 32-bit or 64-bit general-purpose registers (GPRs) for integer operations. * ''64'' × 128-bit vector scalar registers (VSRs) for vector operations and floating-point operations. ** ''32'' × 64-bit floating-point registers (FPRs) as part of the VSRs for floating-point operations. ** ''32'' × 128-bit vector registers (VRs) as part of the VSRs for vector operations. * ''8'' × 4-bit condition register fields (CRs) for comparison and

control flow In computer science, control flow (or flow of control) is the order in which individual statements, instructions or function calls of an imperative program are executed or evaluated. The emphasis on explicit control flow distinguishes an '' ...

. * ''11'' special registers of various sizes: Counter Register (CTR), link register (LR), time base (TBU, TBL), alternate time base (ATBU, ATBL), accumulator (ACC),

status register A status register, flag register, or condition code register (CCR) is a collection of status Flag (computing), flag bits for a Central processing unit, processor. Examples of such registers include FLAGS register (computing), FLAGS register in the ...

s (XER, FPSCR, VSCR, SPEFSCR). Instructions up to version 3.0 have a length of 32 bits, with the exception of the VLE (variable-length encoding) subset that provides for higher code density for low-end embedded applications, and version 3.1 which introduced prefixing to create 64-bit instructions. Most instructions are triadic, i.e. have two source operands and one destination. Single- and double-precision

IEEE 754 The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for floating-point arithmetic originally established in 1985 by the Institute of Electrical and Electronics Engineers (IEEE). The standard #Design rationale, add ...

compliant floating-point operations are supported, including additional fused multiply–add (FMA) and decimal floating-point instructions. There are provisions for

single instruction, multiple data Single instruction, multiple data (SIMD) is a type of parallel computer, parallel processing in Flynn's taxonomy. SIMD describes computers with multiple processing elements that perform the same operation on multiple data points simultaneousl ...

(SIMD) operations on integer and floating-point data on up to 16 elements in one instruction. Power ISA has support for

Harvard Harvard University is a private Ivy League research university in Cambridge, Massachusetts, United States. Founded in 1636 and named for its first benefactor, the Puritan clergyman John Harvard, it is the oldest institution of higher lear ...

cache, i.e. split data and instruction caches, and support for unified caches. Memory operations are strictly load/store, but allow for

out-of-order execution In computer engineering, out-of-order execution (or more formally dynamic execution) is an instruction scheduling paradigm used in high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In t ...

. There is also support for both big and little-endian addressing with separate categories for moded and per-page endianness, and support for both

32-bit In computer architecture, 32-bit computing refers to computer systems with a processor, memory, and other major system components that operate on data in a maximum of 32- bit units. Compared to smaller bit widths, 32-bit computers can perform la ...

and

64-bit In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide. Also, 64-bit central processing units (CPU) and arithmetic logic units (ALU) are those that are based on processor registers, a ...

addressing. Different modes of operation include user, supervisor and hypervisor.

Books

The Power ISA specification is divided into five parts, called "books": * ''Book I'' – ''User Instruction Set Architecture'' covers the base instruction set available to the application programmer. Memory reference, flow control, Integer, floating point, numeric acceleration, application-level programming. It includes chapters regarding auxiliary processing units like

digital signal processor A digital signal processor (DSP) is a specialized microprocessor chip, with its architecture optimized for the operational needs of digital signal processing. DSPs are fabricated on metal–oxide–semiconductor (MOS) integrated circuit chips. ...

s (DSPs) and the AltiVec extension. * ''Book II'' – ''Virtual Environment Architecture'' defines the storage model available to the application programmer, including timing, synchronization, cache management, storage features, byte ordering. * ''Book III'' – ''Operating Environment Architecture'' includes exceptions, interrupts, memory management, debug facilities and special control functions. It is divided into two parts. ** ''Book III-S'' – Defines the supervisor instructions used for general-purpose/server implementations. It is mainly the contents of the Book III of the former PowerPC ISA. ** ''Book III-E'' – Defines the supervisor instructions used for embedded applications. It is derived from the former PowerPC Book E. * ''Book VLE'' – ''Variable Length Encoded Instruction Architecture'' defines alternative instructions and definitions from Books I–III, intended for higher instruction density and very-low-end applications. They use 16-bit instructions and big-endian byte ordering.

Compliancy

New in version 3 of the Power ISA is that you don't have to implement the entire specification to be compliant. The sprawl of instructions and technologies has made the complete specification unwieldy, so the OpenPOWER Foundation have decided to enable tiered compliancy. These levels include optional and mandatory requirements, however one common misunderstanding is that there is nothing stopping an implementation from being compliant at a lower level but having additional selected functions from higher levels and custom extensions. It is however recommended that an option be provided to disable any added functions beyond the design's declared subset level. A design must be compliant at its declared subset level to make use of the Foundation's protection regarding use of

intellectual property Intellectual property (IP) is a category of property that includes intangible creations of the human intellect. There are many types of intellectual property, and some countries recognize more than others. The best-known types are patents, co ...

, be it

patent A patent is a type of intellectual property that gives its owner the legal right to exclude others from making, using, or selling an invention for a limited period of time in exchange for publishing an sufficiency of disclosure, enabling discl ...

s or

trademark A trademark (also written trade mark or trade-mark) is a form of intellectual property that consists of a word, phrase, symbol, design, or a combination that identifies a Good (economics and accounting), product or Service (economics), service f ...

s. This is explained in the OpenPOWER EULA. A compliant design must: * Support the ''Base'' architecture * And support at least one of the subsets ** ''SFS'' – Scalar Fixed-point Subset. 129 instructions. Basic fixed point and load/store instructions, which is really the ''Base'' architecture. ** ''SFFS'' – Scalar Fixed-point + Floating-point Subset. 214 instructions. Adding floating-point operations to the Base. ** ''LCS'' – Linux Compliancy Subset. 962 instructions. Intended for server grade Linux, adding features like 64-bit, optional SIMD/VSX, Radix MMU, little-endian mode and hypervisor support. ** ''ACS'' – AIX Compliancy Subset. 1099 instructions. Intended to run AIX, adding features like decimal and quad-precision floating point, big-endian mode and symmetric multiprocessing. * May include any of the features of the LCS and ACS as Optional or pick from the Always Optional features like matrix math and power management. * Optional features, if chosen, must be implemented in their entirety (partial implementation of an Optional feature is not permitted) * May include Custom extensions, specific to the implementation, implemented in the ''Architecture Sandbox''. If the extension is general-purpose enough, the OpenPOWER Foundation asks that implementors submit it as a Request for Comments (RFC) to th
OpenPOWER ISA Workgroup
Note that it is not strictly necessary to join the OpenPOWER Foundation to submit RFCs. * Much may be implemented in either hardware or firmware.

EABI and Linux Compliancy discrepancy

The EABI specifications predate the announcement and creation of the Compliancy subsets. Regarding the Linux Compliancy subset having VSX (SIMD) optional: in 2003–4, 64-bit EABI v1.9 made SIMD optional, but in July 2015, to improve performance for IBM POWER9 systems, SIMD was made mandatory in EABI v2.0. This discrepancy between SIMD being optional in the Linux Compliancy level but mandatory in EABI v2.0 cannot be rectified without considerable effort: backwards incompatibility for

Linux distribution A Linux distribution, often abbreviated as distro, is an operating system that includes the Linux kernel for its kernel functionality. Although the name does not imply product distribution per se, a distro—if distributed on its own—is oft ...

s is not a viable option. At present this leaves new OpenPOWER implementors wishing to run standard Linux distributions having to implement a massive 962 instructions. By contrast, RISC-V RV64GC, the minimum to run Linux, requires only 165.

Specifications

Power ISA v.2.03

The specification for Power ISA v.2.03 is based on the former PowerPC ISA v.2.02 in

POWER5 The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the POWER4. The principal improvements are support for simultaneous multithreading (SMT) and an on-die memory controller. The POWER5 is a dual-core ...

+ and the Book E extension of the

specification. The Book I included five new chapters regarding auxiliary processing units like DSPs and the AltiVec extension. ;Compliant cores * Freescale PowerPC e200, e500 * IBM PowerPC 405,

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, 460, 970,

and

POWER6 The POWER6 is a microprocessor developed by IBM that implemented the Power ISA#Power ISA v.2.05, Power ISA v.2.05. When it became available in systems in 2007, it succeeded the POWER5#POWER5+, POWER5+ as IBM's flagship Power microprocessor. It i ...

Power ISA v.2.04

The specification for Power ISA v.2.04 was finalized in June 2007. It is based on Power ISA v.2.03 and includes changes primarily to the ''Book III-S'' part regarding

virtualization In computing, virtualization (abbreviated v12n) is a series of technologies that allows dividing of physical computing resources into a series of virtual machines, operating systems, processes or containers. Virtualization began in the 1960s wit ...

hypervisor A hypervisor, also known as a virtual machine monitor (VMM) or virtualizer, is a type of computer software, firmware or hardware that creates and runs virtual machines. A computer on which a hypervisor runs one or more virtual machines is called ...

functions, logical partitioning and virtual page handling. ;Compliant cores * All cores that comply with prior versions of the Power ISA * The PA6T core from P.A. Semi *

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from AMCC

Power ISA v.2.05

The specification for Power ISA v.2.05 was released in December 2007. It is based on Power ISA v.2.04 and includes changes primarily to ''Book I'' and ''Book III-S'', including significant enhancements such as decimal arithmetic ( Decimal Floating-Point in ''Book I'') and server hypervisor improvements. ;Compliant cores * All cores that comply with prior versions of the Power ISA *

* PowerPC 476

Power ISA v.2.06

The specification for Power ISA v.2.06 was released in February 2009, and revised in July 2010. It is based on Power ISA v.2.05 and includes extensions for the POWER7 processor and e500-mc core. One significant new feature is vector-scalar floating-point instructions ( VSX). ''Book III-E'' also includes significant enhancement for the embedded specification regarding hypervisor and virtualisation on single and multi core implementations. The spec was revised in November 2010 to the Power ISA v.2.06 revision B spec, enhancing virtualization features. ;Compliant cores * All cores that comply with prior versions of the Power ISA * POWER7 * A2I * e500-mc * e5500 * e6500

Power ISA v.2.07

The specification for Power ISA v.2.07 was released in May 2013. It is based on Power ISA v.2.06 and includes major enhancements to logical partition functions,

transactional memory In computer science and computer engineering, engineering, transactional memory attempts to simplify concurrent programming by allowing a group of load and store instructions to execute in an linearizability, atomic way. It is a concurrency control ...

, expanded performance monitoring, new storage control features, additions to the VMX and VSX vector facilities (VSX-2), along with AES and Galois Counter Mode (GCM), SHA-224, SHA-256, SHA-384 and SHA-512 (

SHA-2 SHA-2 (Secure Hash Algorithm 2) is a set of cryptographic hash functions designed by the United States National Security Agency (NSA) and first published in 2001. They are built using the Merkle–Damgård construction, from a one-way compression ...

) cryptographic extensions and

cyclic redundancy check A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to digital data. Blocks of data entering these systems get a short ''check value'' attached, based on ...

(CRC)

algorithm In mathematics and computer science, an algorithm () is a finite sequence of Rigour#Mathematics, mathematically rigorous instructions, typically used to solve a class of specific Computational problem, problems or to perform a computation. Algo ...

s. The spec was revised in April 2015 to the Power ISA v.2.07 B spec. ;Compliant cores * All cores that comply with prior versions of the Power ISA *

POWER8 POWER8 is a family of superscalar multi-core microprocessors based on the Power ISA, announced in August 2013 at the Hot Chips conference. The designs are available for licensing under the OpenPOWER Foundation, which is the first time for suc ...

* A2O

Power ISA v.3.0

The specification for Power ISA v.3.0Announcing a New Era of Openness with Power 3.0
/ref> was released in November 2015. It is the first to come out after the founding of the OpenPOWER Foundation and includes enhancements for a broad spectrum of workloads and removes the server and embedded categories while retaining backwards compatibility and adds support for VSX-3 instructions. New functions include 128-bit quad-precision floating-point operations, a

random number generator Random number generation is a process by which, often by means of a random number generator (RNG), a sequence of numbers or symbols is generated that cannot be reasonably predicted better than by random chance. This means that the particular ou ...

, hardware-assisted garbage collection and hardware-enforced trusted computing. The spec was revised in March 2017 to the Power ISA v.3.0 B spec, and revised again to v3.0C in May 2020. One major change from v3.0 to v3.0B is the removal of support for hardware assisted garbage collection. The key difference between v3.0B and v3.0C is that the Compliancy Levels listed in v3.1 were also added to v3.0C. ;Compliant cores * All cores that comply with prior versions of the Power ISA * POWER9 * OpenPOWER Microwatt * Libre-SOC is aiming for Embedded FP compliancy with Power ISA 3.0 only

Power ISA v.3.1

The specification for Power ISA v.3.1 was released in May 2020. Mainly giving support for new functions introduced in Power10, but also includes the notion of optionality to the PowerISA specification. Instructions can now be eight

byte The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of bits used to encode a single character of text in a computer and for this reason it is the smallest addressable un ...

s long, "prefixed instructions", compared to the usual four byte "word instructions". A lot of new functions to SIMD and VSX instructions are also added. VSX and the SVP64 extension provide hardware support for 16-bit half precision floats. One key benefit of the new 64-bit prefixed instructions is the extension of immediates in branches to 34-bit. The spec was revised in September 2021 to the Power ISA v.3.1B spec. The spec was revised in May 2024 to the Power ISA v.3.1C spec. ;Compliant cores * All cores that comply with prior versions of the Power ISA * Power10

References

{{Processor technologies Instruction set architectures Computer-related introductions in 2006 IBM computer hardware Freescale Semiconductor Open microprocessors

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