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Incisive is a suite of tools from
Cadence Design Systems Cadence Design Systems, Inc. (stylized as cādence)Investor's Business DailCEO Lip-Bu Tan Molds Troubled Cadence Into Long-Term LeaderRetrieved November 12, 2020 is an American multinational corporation, multinational technology and computational ...
related to the design and verification of
ASIC An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-efficien ...
s,
SoC SOC, SoC, Soc, may refer to: Science and technology * Information security operations center, in an organization, a centralized unit that deals with computer security issues * Selectable output control * Separation of concerns, a program design pr ...
s, and
FPGA A field-programmable gate array (FPGA) is a type of configurable integrated circuit that can be repeatedly programmed after manufacturing. FPGAs are a subset of logic devices referred to as programmable logic devices (PLDs). They consist of a ...
s. ''Incisive'' is commonly referred to by the name NCSim in reference to the core simulation engine. In the late 1990s, the tool suite was known as ''ldv (logic design and verification)''. Depending on the design requirements, ''Incisive'' has many different bundling options of the following tools: {, class="wikitable" !Tool!!command!!description , - , NC Verilog , ncvlog , Compiler for
Verilog Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits, with the highest level of abstraction being at the re ...
95, Verilog 2001,
SystemVerilog SystemVerilog, standardized as IEEE 1800 by the Institute of Electrical and Electronics Engineers (IEEE), is a hardware description and hardware verification language commonly used to model, design, simulate, test and implement electronic sy ...
and
Verilog-AMS Verilog-AMS is a derivative of the Verilog hardware description language that includes Analog and Mixed-Signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Veril ...
, - , NC VHDL , ncvhdl , Compiler for
VHDL VHDL (Very High Speed Integrated Circuit Program, VHSIC Hardware Description Language) is a hardware description language that can model the behavior and structure of Digital electronics, digital systems at multiple levels of abstraction, ran ...
87, VHDL 93 , - , NC SystemC , ncsc , Compiler for
SystemC SystemC is a set of C++ classes and macros which provide an event-driven simulation interface (see also discrete event simulation). These facilities enable a designer to ''simulate'' concurrent processes, each described using plain C++ synta ...
, - , NC Elaborator , ncelab , Unified linker / elaborator for Verilog, VHDL, and SystemC libraries. Generates a simulation object file referred to as a ''snapshot image''. , - , NC Sim , ncsim , Unified simulation engine for Verilog, VHDL, and SystemC. Loads snapshot images generated by NC Elaborator. This tool can be run in GUI mode or batch command-line mode. In GUI mode, ncsim is similar to the debug features of
ModelSim ModelSim is a multi-language environment by Siemens (previously developed by Mentor Graphics,) for simulation of hardware description languages such as VHDL, Verilog and SystemC, and includes a built-in C debugger.
's vsim. , - , Irun , irun , Executable for single step invocation. Calls ncvlog/ncvhdl/ncsc automatically depending on given files and their extensions. Afterwards ncelab and ncsim are executed. , - , Sim Vision , simvision , A standalone graphical waveform viewer and netlist tracer. This is very similar to
Novas Software Synopsys, Inc. is an American electronic design automation (EDA) company headquartered in Sunnyvale, California, that focuses on silicon design and verification, silicon intellectual property and software security and quality. Synopsys suppl ...
's Debussy.


See also

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List of HDL simulators HDL simulators are software packages that simulate expressions written in one of the hardware description languages, such as VHDL, Verilog, SystemVerilog. This page is intended to list current and historical HDL simulators, accelerators, emulat ...
Electronic design automation software Logic design