History
The basic principle of this kind ofComposition
upright=1.2, Photomicrograph of two metal-gate MOSFETs in a test pattern. Probe pads for two gates and three source/drain nodes are labeled. Usually theOperation
upright=1.2, Metal-oxide-semiconductor structure on p-type siliconMetal-oxide-semiconductor structure
The traditional metal-oxide-semiconductor (MOS) structure is obtained by growing a layer ofMOS capacitors and band diagrams
The MOS capacitor structure is the heart of the MOSFET. Consider a MOS capacitor where the silicon base is of p-type. If a positive voltage is applied at the gate, holes which are at the surface of the p-type substrate will be repelled by the electric field generated by the voltage applied. At first, the holes will simply be repelled and what will remain on the surface will be immobile (negative) atoms of the acceptor type, which creates a depletion region on the surface. Remember that a hole is created by an acceptor atom, e.g. Boron, which has one less electron than Silicon. One might ask how can holes be repelled if they are actually non-entities? The answer is that what really happens is not that a hole is repelled, but electrons are attracted by the positive field, and fill these holes, creating a depletion region where no charge carriers exist because the electron is now fixed onto the atom and immobile. As the voltage at the gate increases, there will be a point at which the surface above the depletion region will be converted from p-type into n-type, as electrons from the bulk area will start to get attracted by the larger electric field. This is known as ''inversion''. The threshold voltage at which this conversion happens is one of the most important parameters in a MOSFET. In the case of a p-type bulk, inversion happens when the intrinsic energy level at the surface becomes smaller than theStructure and channel formation
upright=1.5, ''Channel formation in nMOS MOSFET shown as band diagram'': Top panels: An applied gate voltage bends bands, depleting holes from surface (left). The charge inducing the bending is balanced by a layer of negative acceptor-ion charge (right). Bottom panel: A larger applied voltage further depletes holes but conduction band lowers enough in energy to populate a conducting channel file:Illustration of C-V measurement.gif, upright=1.5, C–V profile for a bulk MOSFET with different oxide thickness. The leftmost part of the curve corresponds to accumulation. The valley in the middle corresponds to depletion. The curve on the right corresponds to inversion A MOSFET is based on the modulation of charge concentration by a MOS capacitance between a ''body'' electrode and a ''gate'' electrode located above the body and insulated from all other device regions by a gate dielectric layer. If dielectrics other than an oxide are employed, the device may be referred to as a metal-insulator-semiconductor FET (MISFET). Compared to the MOS capacitor, the MOSFET includes two additional terminals (''source'' and ''drain''), each connected to individual highly doped regions that are separated by the body region. These regions can be either p or n type, but they must both be of the same type, and of opposite type to the body region. The source and drain (unlike the body) are highly doped as signified by a "+" sign after the type of doping. If the MOSFET is an n-channel or nMOS FET, then the source and drain are ''n+'' regions and the body is a ''p'' region. If the MOSFET is a p-channel or pMOS FET, then the source and drain are ''p+'' regions and the body is a ''n'' region. The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel. The occupancy of the energy bands in a semiconductor is set by the position of theModes of operation
file:MOSFET functioning.svg, upright=2, Source tied to the body to ensure no body bias:Body effect
upright=1.2, Band diagram showing body effect. ''V''SB splits Fermi levels Fn for electrons and Fp for holes, requiring larger ''V''GB to populate the conduction band in an nMOS MOSFET The occupancy of the energy bands in a semiconductor is set by the position of the Fermi level#"Fermi level" in semiconductor physics, Fermi level relative to the semiconductor energy-band edges. Application of a source-to-substrate reverse bias of the source-body pn-junction introduces a split between the Fermi levels for electrons and holes, moving the Fermi level for the channel further from the band edge, lowering the occupancy of the channel. The effect is to increase the gate voltage necessary to establish the channel, as seen in the figure. This change in channel strength by application of reverse bias is called the 'body effect'. Simply put, using an nMOS example, the gate-to-body bias ''V''GB positions the conduction-band energy levels, while the source-to-body bias VSB positions the electron Fermi level near the interface, deciding occupancy of these levels near the interface, and hence the strength of the inversion layer or channel. The body effect upon the channel can be described using a modification of the threshold voltage, approximated by the following equation: : where ''V''TB is the threshold voltage with substrate bias present, and ''V''T0 is the zero-''V''SB value of threshold voltage, is the body effect parameter, and 2''φ''B is the approximate potential drop between surface and bulk across the depletion layer when and gate bias is sufficient to ensure that a channel is present. For a uniformly doped p-type substrate with bulk acceptor doping of ''NA'' per unit volume, : with ''ni'' the intrinsic mobile carrier density per unit volume in the bulk. See, for example, As this equation shows, a reverse bias causes an increase in threshold voltage ''V''TB and therefore demands a larger gate voltage before the channel populates. The body can be operated as a second gate, and is sometimes referred to as the "back gate"; the body effect is sometimes called the "back-gate effect".Circuit symbols
A variety of symbols are used for the MOSFET. The basic design is generally a line for the channel with the source and drain leaving it at right angles and then bending back at right angles into the same direction as the channel. Sometimes three line segments are used forApplications
DigitalMOS integrated circuits
Following the development ofCMOS circuits
The MOSFET is used in digital complementary metal-oxide-semiconductor (Digital
The growth of digital technologies like theAnalog
The MOSFET's advantages in digital circuits do not translate into supremacy in all analog circuits. The two types of circuit draw upon different features of transistor behavior. Digital circuits switch, spending most of their time either fully on or fully off. The transition from one to the other is only of concern with regards to speed and charge required. Analog circuits depend on operation in the transition region where small changes to ''V'' can modulate the output (drain) current. The JFET andAnalog switches
MOSFET analog switches use the MOSFET to pass analog signals when on, and as a high impedance when off. Signals flow in both directions across a MOSFET switch. In this application, the drain and source of a MOSFET exchange places depending on the relative voltages of the source/drain electrodes. The source is the more negative side for an N-MOS or the more positive side for a P-MOS. All of these switches are limited on what signals they can pass or stop by their gate-source, gate-drain and source–drain voltages; exceeding the voltage, current, or power limits will potentially damage the switch.Single-type
This analog switch uses a four-terminal simple MOSFET of either P or N type. In the case of an n-type switch, the body is connected to the most negative supply (usually GND) and the gate is used as the switch control. Whenever the gate voltage exceeds the source voltage by at least a threshold voltage, the MOSFET conducts. The higher the voltage, the more the MOSFET can conduct. An N-MOS switch passes all voltages less than ''V'' − ''V''. When the switch is conducting, it typically operates in the linear (or ohmic) mode of operation, since the source and drain voltages will typically be nearly equal. In the case of a P-MOS, the body is connected to the most positive voltage, and the gate is brought to a lower potential to turn the switch on. The P-MOS switch passes all voltages higher than ''V'' − ''V'' (threshold voltage ''V'' is negative in the case of enhancement-mode P-MOS).Dual-type (CMOS)
This "complementary" or CMOS type of switch uses one P-MOS and one N-MOS FET to counteract the limitations of the single-type switch. The FETs have their drains and sources connected in parallel, the body of the P-MOS is connected to the high potential (''V''DD) and the body of the N-MOS is connected to the low potential (''gnd''). To turn the switch on, the gate of the P-MOS is driven to the low potential and the gate of the N-MOS is driven to the high potential. For voltages between ''V''DD − ''V''tn and ''gnd'' − ''V''tp, both FETs conduct the signal; for voltages less than ''gnd'' − ''V''tp, the N-MOS conducts alone; and for voltages greater than ''V''DD − ''V''tn, the P-MOS conducts alone. The voltage limits for this switch are the gate-source, gate-drain and source-drain voltage limits for both FETs. Also, the P-MOS is typically two to three times wider than the N-MOS, so the switch will be balanced for speed in the two directions. Tri-state circuitry sometimes incorporates a CMOS MOSFET switch on its output to provide for a low-ohmic, full-range output when on, and a high-ohmic, mid-level signal when off.Construction
Gate material
The primary criterion for the gate material is that it is a good conductor. Highly dopedInsulator
As devices are made smaller, insulating layers are made thinner, often through steps of thermal oxidation or localised oxidation of silicon ( LOCOS). For nano-scaled devices, at some point tunneling of carriers through the insulator from the channel to the gate electrode takes place. To reduce the resulting leakage current, the insulator can be made thinner by choosing a material with a higher dielectric constant. To see how thickness and dielectric constant are related, note thatJunction design
The source-to-body and drain-to-body junctions are the object of much attention because of three major factors: their design affects the current-voltage (''I-V'') characteristics of the device, lowering output resistance, and also the speed of the device through the loading effect of the junctionScaling
upright=1.2, Trend of Intel CPU transistor gate length upright=1.2, MOSFET version of gain-boosted current mirror; M1 and M2 are in active mode, while M3 and M4 are in Ohmic mode, and act like resistors. The operational amplifier provides feedback that maintains a high output resistance. Over the past decades, the MOSFET (as used for digital logic) has continually been scaled down in size; typical MOSFET channel lengths were once severalOther types
Dual-gate
upright=1.2, A ">FinFET The dual-gate MOSFET has a tetrode configuration, where both gates control the current in the device. It is commonly used for small-signal devices in radio frequency applications where biasing the drain-side gate at constant potential reduces the gain loss caused byDepletion-mode
There are ''depletion-mode'' MOSFET devices, which are less commonly used than the standard ''enhancement-mode'' devices already described. These are MOSFET devices that are doped so that a channel exists even with zero voltage from gate to source. To control the channel, a negative voltage is applied to the gate (for an n-channel device), depleting the channel, which reduces the current flow through the device. In essence, the depletion-mode device is equivalent to aMetal-insulator-semiconductor field-effect transistor (MISFET)
Metal-insulator-semiconductor field-effect-transistor, or ''MISFET'', is a more general term than ''MOSFET'' and a synonym to ''insulated-gate field-effect transistor'' (IGFET). All MOSFETs are MISFETs, but not all MISFETs are MOSFETs. The gate dielectric insulator in a MISFET isNMOS logic
For devices of equal current driving capability, n-channel MOSFETs can be made smaller than p-channel MOSFETs, due to p-channel charge carriers ( holes) having lowerPower MOSFET
upright=1.2, Cross section of a power MOSFET, with square cells. A typical transistor is constituted of several thousand cellsDouble-diffused metal-oxide-semiconductor (DMOS)
There are ''Radiation-hardened-by-design (RHBD)
Semiconductor sub-micrometer and nanometer electronic circuits are the primary concern for operating within the normal tolerance in harshSee also
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External links