Opteron is the name of a
central processing unit
A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, a ...
(CPU) family within the
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
line. Designed by
Advanced Micro Devices
Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufact ...
(AMD) for the
server market,
Opteron competed with Intel's
Xeon
Xeon ( ) is a brand of x86 microprocessors designed, manufactured, and marketed by Intel, targeted at the non-consumer workstation, server, and embedded system markets. It was introduced in June 1998. Xeon processors are based on the same arc ...
. The Opteron family is succeeded by the
Zen-based Epyc, and
Ryzen Threadripper
Ryzen ( ) is a brand of multi-core x86-64 microprocessors designed and marketed by AMD for desktop, mobile, server, and embedded platforms based on the Zen microarchitecture. It consists of central processing units (CPUs) marketed for mainstr ...
and Threadripper Pro series.
For Socket 940 and Socket 939 Opterons, each chip has a three-digit model number, in the form ''Opteron XYY''. For Socket F and Socket AM2 Opterons, each chip has a four-digit model number, in the form ''Opteron XZYY''. For all Opterons, the first digit (the X) specifies the number of CPUs on the target machine:
* 1 – has 1 processor (uniprocessor)
* 2 – has 2 processors (dual processor)
* 8 – has 4 or 8 processors
For Socket F and Socket AM2 Opterons, the second digit (the Z) represents the processor generation. Presently, only 2 (dual-core), DDR2, 3 (quad-core) and 4 (six-core) are used.
For all Opterons, the last two digits in the model number (the YY) indicate the
clock rate
In computing, the clock rate or clock speed typically refers to the frequency at which the clock generator of a processor can generate pulses, which are used to synchronize the operations of its components, and is used as an indicator of the p ...
(frequency) of a CPU, a higher number indicating a higher clock rate. This speed indication is comparable to processors of the same generation if they have the same amount of cores. Single-cores and dual-cores have different indications, despite sometimes having the same clock rate.
Model number methodology for the AMD Opteron 4000 and 6000 Series processors.
AMD Opteron processors are identified by a four digit model number, ''ZYXX'', where:
Z – denotes product series
* 4000 Series = Low cost and power optimized 1- and 2-way servers
* 6000 Series = High performance 2- and 4-way servers
Y – denotes series generation
* 41xx = 1st generation of 4000 series
* 61xx = 1st generation of 6000 series
XX – communicates a change in product specifications within the series, and is not a relative measure of performance.
The suffix HE or EE denotes a high-efficiency or energy-efficiency model with a lower
thermal design power (TDP) than a standard Opteron. The suffix SE denotes a top-of-the-line model with a higher TDP than a standard Opteron.
Feature overview
CPUs
CPU features table
APUs
APU features table
K8 based Opterons
First Generation Opterons
Opteron 100-series "SledgeHammer" (130 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
* All models with OPN ending in AG support up to Registered PC2700
DDR SDRAM
* All other models support up to Registered PC3200
DDR SDRAM
* All models only support single-processor configurations
Opteron 200-series "SledgeHammer" (130 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
* All models with OPN ending in AH support up to Registered PC2700
DDR SDRAM
* All other models support up to Registered PC3200
DDR SDRAM
* All models support up to two-processor configurations
Opteron 800-series "SledgeHammer" (130 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
* All models with OPN ending in AI support up to Registered PC2700
DDR SDRAM
* All other models support up to Registered PC3200
DDR SDRAM
* All models support up to eight-processor configurations
Opteron 100-series "Venus" (90 nm, socket 939)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
* All models support up to Unbuffered PC3200
DDR SDRAM
* All models only support single-processor configurations
Opteron 100-series "Venus" (90 nm, socket 940)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
* All models support up to Registered PC3200
DDR SDRAM
* All models only support single-processor configurations
Opteron 200-series "Troy" (90 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
* All models support up to Registered PC3200
DDR SDRAM
* All models support up to two-processor configurations
Opteron 800-series "Athens" (90 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
* All models support up to Registered PC3200
DDR SDRAM
* All models support up to eight-processor configurations
Opteron 100-series "Denmark" (90 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
* All models support up to Unbuffered PC3200
DDR SDRAM
* All models only support single-processor configurations
Opteron 200-series "Italy" (90 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
* All models support up to Registered PC3200
DDR SDRAM
* All models support up to two-processor configurations
Opteron 800-series "Egypt" (90 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
''
* All models support up to Registered PC3200
DDR SDRAM
* All models support up to eight-processor configurations
Second Generation Opterons
Opteron 1200-series "Santa Ana" (90 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
''
* All models support up to Unbuffered PC2-6400
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DD ...
* All models only support single-processor configurations
Opteron 2200-series "Santa Rosa" (90 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
''
* All models support up to Registered PC2-5300
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DD ...
* All models support up to two-processor configurations
Opteron 8200-series "Santa Rosa" (90 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
''
* All models support up to Registered PC2-5300
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DD ...
* All models support up to eight-processor configurations
K10 based Opterons
Third Generation Opterons
Opteron 1300-series "Budapest" (65 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
(SVM & Rapid Virtualization Indexing)''
* All models support up to Unbuffered PC2-6400
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DD ...
* All models support single-processor configurations
* B2-Stepping does have the TLB-Bug (
Translation Lookaside Buffer, see also AMD "errata number 298")
Opteron 2300-series "Barcelona" (65 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
(SVM & Rapid Virtualization Indexing)''
* All models support up to Registered PC2-5300
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DD ...
* All models support up to two-processor configurations
Opteron 8300-series "Barcelona" (65 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
(SVM & Rapid Virtualization Indexing)''
* All models support up to Registered PC2-5300
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DD ...
* All models support up to eight-processor configurations
Opteron 1300-series "Suzuka" (45 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
(SVM & Rapid Virtualization Indexing)''
* All models support up to Unbuffered PC3-10600
DDR3 SDRAM
Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-spee ...
* All models support single-processor configurations
115W
TDP Page 54 http://support.amd.com/us/Processor_TechDocs/43374.pdf
Opteron 2300-series "Shanghai" (45 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
(SVM & Rapid Virtualization Indexing)''
* All models support up to Registered PC2-6400
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DD ...
* All models support up to two-processor configurations
Opteron 8300-series "Shanghai" (45 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
(SVM & Rapid Virtualization Indexing)''
* All models support up to Registered PC2-6400
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DD ...
* All models support up to eight-processor configurations
Opteron 2400-series "Istanbul" (45 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
(SVM & Rapid Virtualization Indexing),
HT-Assist''
* All models support up to Registered PC2-6400
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DD ...
* All models support up to two-socket configurations
Opteron 8400-series "Istanbul" (45 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
(SVM & Rapid Virtualization Indexing),
HT-Assist''
* All models support up to Registered PC2-6400
DDR2 SDRAM
Double Data Rate 2 Synchronous Dynamic Random-Access Memory (DDR2 SDRAM) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) interface. It superseded the original DDR SDRAM specification, and was itself superseded by DD ...
* All models support up to eight-processor configurations
* Istanbul models have 6 MB of L3 cache but only 5 MB are visible with the HT Assist feature activated using 1 MB as a directory cache.
4100- & 6100-series Opterons
Opteron 4100-series "Lisbon" (45 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
Cool'n'Quiet
AMD Cool'n'Quiet is a CPU dynamic frequency scaling and power saving technology introduced by AMD with its Athlon XP processor line. It works by reducing the processor's clock rate and voltage when the processor is idle. The aim of this technolog ...
'', ''
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
''
* All models support up to two
socket
Socket may refer to:
Mechanics
* Socket wrench, a type of wrench that uses separate, removable sockets to fit different sizes of nuts and bolts
* Socket head screw, a screw (or bolt) with a cylindrical head containing a socket into which the hexag ...
configurations
* Memory support: Up to 4
DIMM
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal computers, ...
s per socket
* Memory controller: Two channels of
UDDR3, RDDR3 up to PC3-10667
* Lisbon models have 6MB of L3 cache but only 5 MB are visible when the HT Assist feature is activated, using 1 MB as directory cache.
Opteron 6100-series "Magny-Cours" (45 nm)
* All models support: ''
MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
,
SSE,
SSE2,
SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
,
SSE4a, Enhanced
3DNow!
3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...
,
NX bit,
AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
,
Cool'n'Quiet
AMD Cool'n'Quiet is a CPU dynamic frequency scaling and power saving technology introduced by AMD with its Athlon XP processor line. It works by reducing the processor's clock rate and voltage when the processor is idle. The aim of this technolog ...
'', ''
AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
(SVM & Rapid Virtualization Indexing),
HT-Assist''
* All models support two or four
socket
Socket may refer to:
Mechanics
* Socket wrench, a type of wrench that uses separate, removable sockets to fit different sizes of nuts and bolts
* Socket head screw, a screw (or bolt) with a cylindrical head containing a socket into which the hexag ...
configurations
[
* Memory support: Up to 12 ]DIMM
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal computers, ...
s per socket[
* Memory controller: Four channels of UDDR3, RDDR3 up to PC3-10667][
]
* Magny-Cours models have 12 MB of L3 cache (2 × 6 MB) but only 10 MB is visible with the HT Assist feature activated using 2 MB as a directory cache.
Bulldozer based Opterons
3200-, 4200- & 6200-series Opterons
Opteron 3200-series "Zurich" (32 nm)
* All models support: ''MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
, SSE, SSE2, SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitectur ...
, SSE4.1
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, SSE4.2, SSE4a, IOMMU, NX bit, AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
, AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, AES, CLMUL, AVX, CVT16– F16C, XOP, FMA4.''
* All models support single socket
Socket may refer to:
Mechanics
* Socket wrench, a type of wrench that uses separate, removable sockets to fit different sizes of nuts and bolts
* Socket head screw, a screw (or bolt) with a cylindrical head containing a socket into which the hexag ...
configurations
* Memory support: Up to 4 DIMM
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal computers, ...
s per socket
* Memory controller: Two channels of UDDR3, RDDR3 up to PC3-15000
* Die size: 315 mm²
Opteron 4200-series "Valencia" (32 nm)
* All models support: ''MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
, SSE, SSE2, SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitectur ...
, SSE4.1
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, SSE4.2, SSE4a, NX bit, AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
, AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, AES, CLMUL, AVX, XOP, FMA4.''
* All models support up to two socket
Socket may refer to:
Mechanics
* Socket wrench, a type of wrench that uses separate, removable sockets to fit different sizes of nuts and bolts
* Socket head screw, a screw (or bolt) with a cylindrical head containing a socket into which the hexag ...
configurations
* Memory support: Up to 4 DIMM
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal computers, ...
s per socket
* Memory controller: Two channels of UDDR3, RDDR3 up to PC3-12800
Opteron 6200-series "Interlagos" (32 nm)
* All models support: ''MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
, SSE, SSE2, SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitectur ...
, SSE4.1
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, SSE4.2, SSE4a, NX bit, AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
, AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, AES, CLMUL, AVX, XOP, FMA4.''
* All models support two or four socket
Socket may refer to:
Mechanics
* Socket wrench, a type of wrench that uses separate, removable sockets to fit different sizes of nuts and bolts
* Socket head screw, a screw (or bolt) with a cylindrical head containing a socket into which the hexag ...
configurations
* Memory support: Up to 12 DIMM
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal computers, ...
s per socket
* Memory controller: Four channels of UDDR3, RDDR3 up to PC3-12800
* Interlagos models have 16 MB of L3 cache (2x8 MB) but only 14 MB is visible with the HT Assist feature activated using 2 MB as a directory cache.
Piledriver based Opterons
3300-, 4300- & 6300-series Opterons
Opteron 3300-series "Delhi" (32 nm)
* All models support: ''MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
, SSE, SSE2, SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitectur ...
, SSE4.1
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, SSE4.2, SSE4a, NX bit, AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
, AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, CVT16– F16C, AMD Turbo Core3.0., ECC''
* All models support single socket
Socket may refer to:
Mechanics
* Socket wrench, a type of wrench that uses separate, removable sockets to fit different sizes of nuts and bolts
* Socket head screw, a screw (or bolt) with a cylindrical head containing a socket into which the hexag ...
configurations
* Memory support: Up to 4 DIMM
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal computers, ...
s per socket
* Memory controller: Two channels of UDDR3, RDDR3 up to PC3-15000
* Die size: 315 mm²
Opteron 4300-series "Seoul" (32 nm)
* All models support: ''MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
, SSE, SSE2, SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitectur ...
, SSE4.1
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, SSE4.2, SSE4a, NX bit, AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
, AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, AES, CLMUL, AVX, AVX 1.1, XOP, FMA3, FMA4, CVT16– F16C, AMD Turbo Core, ECC
* All models support up to two socket
Socket may refer to:
Mechanics
* Socket wrench, a type of wrench that uses separate, removable sockets to fit different sizes of nuts and bolts
* Socket head screw, a screw (or bolt) with a cylindrical head containing a socket into which the hexag ...
configurations
* Memory support: Up to 4 DIMM
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal computers, ...
s per socket
* Memory controller: Two channels of UDDR3, RDDR3 up to PC3-15000
Opteron 6300-series "Abu Dhabi" (32 nm)
* All models support: ''MMX MMX may refer to:
* 2010, in Roman numerals
Science and technology
* MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel
* MMX Mineração, a Brazilian mining company
* Martian Moons eXploration, a Japane ...
, SSE, SSE2, SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitectur ...
, SSE4.1
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, SSE4.2, SSE4a, NX bit, AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
, AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, IOMMU, AES, CLMUL, AVX, AVX 1.1, BMI1 (Bit Manipulation Instructions 1), ABM (Advanced Bit Manipulation), TBM (Trailing Bit Manipulation instructions), XOP, FMA3, FMA4, CVT16– F16C, Turbo Core 2.0, EVP (Enhanced Virus Protection), ECC''
* All models support two or four socket
Socket may refer to:
Mechanics
* Socket wrench, a type of wrench that uses separate, removable sockets to fit different sizes of nuts and bolts
* Socket head screw, a screw (or bolt) with a cylindrical head containing a socket into which the hexag ...
configurations
* Memory support: Up to 12 DIMM
A DIMM () (Dual In-line Memory Module), commonly called a RAM stick, comprises a series of dynamic random-access memory integrated circuits. These memory modules are mounted on a printed circuit board and designed for use in personal computers, ...
s per socket
* Memory controller: Four channels of UDDR3, RDDR3 up to PC3-15000
* Abu Dhabi models have 16 MB of L3 cache (2x8 MB) but only 14 MB is visible with the HT Assist feature activated using 2 MB as a directory cache.
* Two new 6300 models code-named "Warsaw" were added in 2014 (6338P and 6370P) that operate at lower clock frequencies using less power.
Excavator based Opterons
X3000-series Opterons
Opteron X3000-series "Toronto" (28 nm)
* All models support: MMX, SSE, SSE2, SSE3
SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...
, SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
History
SSSE3 was first introduced with Intel processors based on the Core microarchitectur ...
, SSE4.1
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, SSE4.2, SSE4a, AMD64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...
, AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, AES, CLMUL, AVX, AVX 1.1, AVX2, XOP, FMA3, FMA4, F16C, ABM
ABM or Abm may refer to:
Companies
* ABM Industries, a US facility management provider
* ABM Intelligence, a UK software company
* Advantage Business Media, a US digital marketing and information services company
* Associated British Maltsters, ...
, BMI1
Polycomb complex protein BMI-1 also known as polycomb group RING finger protein 4 (PCGF4) or RING finger protein 51 (RNF51) is a protein that in humans is encoded by the ''BMI1'' gene (B cell-specific Moloney murine leukemia virus integration ...
, BMI2
Bit manipulation instructions sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions ...
, TBM, RDRAND
* Two or Four CPU cores based on the Excavator
Excavators are heavy construction equipment consisting of a boom, dipper (or stick), bucket and cab on a rotating platform known as the "house". The house sits atop an undercarriage with tracks or wheels. They are a natural progression fro ...
microarchitecture
* L1 Cache: 32 KB Data per core and 96 KB Instructions per module
* Memory controller: Two channels of DDR4 SDRAM
Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high Bandwidth (computing), bandwidth ("double data rate") interface.
Released to the market in 2014, it is a v ...
up to PC4-19200
* GPU based on Graphics Core Next (GCN) 3rd Generation architecture
Jaguar-based Opterons
X1100 and X2100 series Opterons
Opteron X1100-series "Kyoto" (28nm)
* Socket FT3 (BGA)
* 4 CPU cores ( Jaguar (microarchitecture))
* SSE4.1, SSE4.2, AVX, AES, F16C, BMI1, AMD-V
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU.
In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...
, AMD-P (power management) support
* Turbo Dock Technology, C6 and CC6 low power states
* 128-bit FPU FPU may stand for:
Universities
* Florida Polytechnic University, in Lakeland, Florida, United States
* Franklin Pierce University, in New Hampshire, United States
* Fresno Pacific University, in California, United States
* Fukui Prefectural Un ...
Opteron X2100-series "Kyoto" (28nm)
* Socket FT3 (BGA)
* 4 CPU cores ( Jaguar (microarchitecture))
* SSE4.1, SSE4.2, AVX, AES, F16C, BMI1 support
* Turbo Dock Technology, C6 and CC6 low power states
* GPU based on Graphics Core Next
Graphics Core Next (GCN) is the codename for a series of microarchitectures and an instruction set architecture that were developed by AMD for its GPUs as the successor to its TeraScale microarchitecture. The first product featuring GCN was laun ...
(GCN) architecture
ARM Cortex A57 based Opterons
Opteron A1100-series "Seattle" (28nm)
The AMD Opteron A1100 is an enterprise-class ARM Cortex-A57-based SOC.
* Up to 64 GB DDR3L-1600 and up to 128GB DDR4-1866 with ECC
* SoC peripherals include 6 × SATA 3, 2 × Integrated 10 GbE LAN and 8 PCI Express lanes in ×8, ×4 and ×2 configurations.
See also
* List of AMD chipsets
This is an overview of chipsets sold under the AMD brand, manufactured before May 2004 by the company itself, before the adoption of open platform approach as well as chipsets manufactured by ATI Technologies after October 2006 as the completion ...
* List of AMD Accelerated Processing Unit microprocessors
* List of AMD Epyc microprocessors
* List of AMD FX microprocessors
AMD FX is a series of AMD microprocessors for personal computers. The following is a list of AMD FX brand microprocessors. Some APUs also carry an FX model name, but the term "FX" normally only refers to CPUs which are not just APUs with the iGP ...
* Table of AMD processors
References
See also
* List of AMD microprocessors
* List of AMD CPU microarchitectures
* List of AMD mobile microprocessors
* List of AMD Athlon microprocessors
* List of AMD Athlon XP microprocessors
* List of AMD Athlon 64 microprocess ...
References
External links
*
AMD Technical Docs
{{AMD CPU sockets
*Opteron
AMD Opteron
Opteron is AMD's x86 former server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture (known generically as x86-64 or AMD64). It was released on April 22, 2003, with the ''SledgeHa ...