Xeon DP, Dual Core

" Sossaman" (65 nm)

* Based on Enhanced Pentium M microarchitecture * All models support: '' MMX, SSE,

SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier SSE ins ...

SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revi ...

, Demand Based Switching (Intel's Server EIST),

XD bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...

(an

NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...

implementation),

Intel VT-x x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...

'' * All models support dual-processor configurations * Die size: 90.3 mm² * Steppings: C0, D0

Sources

* * {{Cite web, url=https://m.hexus.net/tech/news/cpu/4604-intel-yonah-hidden-features-exposed/, title=Intel Yonah hidden features exposed, website=HEXUS.net Intel Xeon (Pentium M)