This article contains information about Intel's GPUs (see Intel Graphics Technology) and motherboard graphics chipsets in table form. In 1982, Intel licensed the NEC μPD7220 and announced it as the Intel 82720 Graphics Display Controller.

First generation

Intel's first generation GPUs:

Second generation

Intel marketed its second generation using the brand Extreme Graphics. These chips added support for texture combiners allowing support for OpenGL 1.3.

Third generation

Intel's first DirectX 9 GPUs with hardware Pixel Shader 2.0 support.

Gen4

The last generation of motherboard integrated graphics. Full hardware DirectX 10 support starting with GMA X3500. * Each EU has a 128-bit wide FPU that natively executes four 32-bit operations per clock cycle.

Gen5

* Integrated graphics chip moved from motherboard into the processor. * Improved gaming performance * Can access CPU's cache * Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle. * Hierarchical-Z compression and fast Z clear

Gen6

* Each EU has a 128-bit wide FPU that natively executes eight 16-bit or four 32-bit operations per clock cycle. * Double peak performance per clock cycle compared to previous generation due to fused multiply-add instruction. * The entire GPU shares a sampler and an ROP.

Gen7

* ¹ FP32 ALUs : EUs : Subslices * Each EU contains 2 × 128-bit FPUs and has double peak performance per clock cycle compared to previous generation. One supports FP32 and FP64, and the other supports only FP32. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. Only one of the FPUs supports 32-bit integer instructions. * Each Subslice contains 6 or 8 (or 10 in Haswell GPUs) EUs and a sampler, and has 64 KB shared memory.

Gen7.5

Gen8

* ¹ FP32 ALUs : EUs : Subslices * Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions is one per 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. * Each Subslice contains 8 EUs and a sampler (4 tex/clk), and has 64 KB shared memory. * Intel Quick Sync Video * For Windows 10, the total system memory that is available for graphics use is half the system memory. For Windows 8, it is up to 3840 MB. On Windows 7, it is up to about 1.7 GB through DVMT.

Gen9

* ¹ FP32 ALUs : EUs : Subslices * Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter (eighth in Apollo Lake) of the FP32 FLOPS. * Each Subslice contains 8 EUs (two of which are disabled in GT1) and a sampler (4 tex/clk), and has 64 KB shared memory. * Intel Quick Sync Video * For Windows 10, the total system memory that is available for graphics use is half the system memory. For Windows 8, it is up to 3840 MB. On Windows 7, it is up to about 1.7 GB through DVMT. * WDDM 2.2 support with Windows Mixed Reality begins with KabyLake-based GPUs.

Gen11

* ¹ FP32 ALUs : EUs : Subslices * Each EU contains 2 x 128-bit FPUs. One supports 32-bit and 64-bit integer, FP16, FP32, FP64, and transcendental math functions, and the other supports only 32-bit and 64-bit integer, FP16 and FP32. Thus the FP16 (or 16-bit integer) FLOPS is twice the FP32 (or 32-bit integer) FLOPS. Since the throughput of FP64 instructions are 2 cycles, the FP64 FLOPS is a quarter of the FP32 FLOPS. * Each Subslice contains 8 EUs and a sampler (4 tex/clk), and has 64 KB shared memory. * Intel Quick Sync Video * For Windows 10, the total system memory that is available for graphics use is half the system memory. * No eDRAM.

Gen12

Intel Xe is a GPGPU and dGPU product line first released in 2020, in the mobile Tiger Lake line and Rocket Lake, Alder Lake and Raptor Lake line. * ¹ FP32 ALUs: EUs: Subslices

Gen 12.5

Gen 12.7

Desktop

Mobile

Workstation

Battlemage based

PowerVR based

Notes

;Acronyms: The following acronyms are used throughout the article. * EU: Execution Unit * iDCT: Inverse discrete cosine transform * iMDCT: Inverse modified discrete cosine transform * LF: In-loop deblocking filter * MC: Motion compensation * VLD: Variable-length code (sometimes referred to as slice-level acceleration) * WMV9: Windows Media Video 9 codec ;Full hardware acceleration techniques: Intel graphic processing units employ the following techniques in hardware acceleration of digital video playback. ;Calculation: The raw performance of integrated GPU, in FLOPS, can be calculated as follows: : :For example, the HD Graphics 3000 is rated at 125 GFLOPS, which is consistent with the formula (12 * 4 * 2 * 1,300 MHz).

References

{{DEFAULTSORT:Intel graphics processing units Graphics processing units Computing comparisons Lists of microprocessors *Intel Graphics processing units Graphics processing units