The AMD Jaguar Family 16h is a low-power microarchitecture designed by AMD. It is used in

APUs Apus is a small constellation in the southern sky. It represents a bird-of-paradise, and its name means "without feet" in Greek because the bird-of-paradise was once wrongly believed to lack feet. First depicted on a celestial globe by Pet ...

succeeding the Bobcat Family microarchitecture in 2013 and being succeeded by AMD's Puma architecture in 2014. It is two-way

superscalar A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a sup ...

and capable of

out-of-order execution In computer engineering, out-of-order execution (or more formally dynamic execution) is a paradigm used in most high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In this paradigm, a proces ...

. It is used in AMD's Semi-Custom Business Unit as a design for custom processors and is used by AMD in four product families: ''Kabini'' aimed at notebooks and mini PCs, ''Temash'' aimed at tablets, ''Kyoto'' aimed at micro-servers, and the ''G-Series'' aimed at embedded applications. Both the

PlayStation 4 The PlayStation 4 (PS4) is a home video game console developed by Sony Interactive Entertainment. Announced as the successor to the PlayStation 3 in February 2013, it was launched on November 15, 2013, in North America, November 29, 2013 i ...

and the

Xbox One The Xbox One is a home video game console developed by Microsoft. Announced in May 2013, it is the successor to Xbox 360 and the third base console in the Xbox series of video game consoles. It was first released in North America, parts of ...

use chips based on the Jaguar microarchitecture, with more powerful GPUs than AMD sells in its own commercially available Jaguar APUs.

Design

* 32 KiB instruction + 32 KiB data L1

cache Cache, caching, or caché may refer to: Places United States * Cache, Idaho, an unincorporated community * Cache, Illinois, an unincorporated community * Cache, Oklahoma, a city in Comanche County * Cache, Utah, Cache County, Utah * Cache County ...

per core, L1 cache includes parity error detection * 16-way, 1–2 MiB unified L2 cache shared by two or four cores, L2 cache is protected from errors by the use of error correcting code *

Out-of-order execution In computer engineering, out-of-order execution (or more formally dynamic execution) is a paradigm used in most high-performance central processing units to make use of instruction cycles that would otherwise be wasted. In this paradigm, a proces ...

and

speculative execution Speculative execution is an optimization technique where a computer system performs some task that may not be needed. Work is done before it is known whether it is actually needed, so as to prevent a delay that would have to be incurred by doing ...

* Integrated

memory controller The memory controller is a digital circuit that manages the flow of data going to and from the computer's main memory. A memory controller can be a separate chip or integrated into another chip, such as being placed on the same die or as an int ...

* Two-way integer execution * Two-way 128-bit wide floating-point and packed integer execution * Integer hardware divider * Consumer processors support two DDR3L DIMMs in one channel at frequencies up to 1600 MHz * Server processors support two DDR3 DIMMs in one channel at frequencies up to 1600 MHz with ECC * As a SoC (not just an APU) it integrates

Fusion controller hub This is an overview of chipsets sold under the AMD brand, manufactured before May 2004 by the company itself, before the adoption of open platform approach as well as chipsets manufactured by ATI Technologies after October 2006 as the completion ...

* Jaguar does ''not'' feature

clustered multi-thread The AMD Bulldozer Family 15h is a microprocessor microarchitecture for the FX and Opteron line of processors, developed by AMD for the desktop and server markets. Bulldozer is the codename for this family of microarchitectures. It was releas ...

(CMT), meaning that execution resources are not shared between cores

Instruction set support

The ''Jaguar'' core has support for the following instruction sets and instructions:

MMX MMX may refer to: * 2010, in Roman numerals Science and technology * MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel * MMX Mineração, a Brazilian mining company * Martian Moons eXploration, a Japane ...

, SSE,

SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier SSE i ...

SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...

SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitectu ...

, SSE4a, SSE4.1, SSE4.2, AVX, F16C, CLMUL, AES, BMI1, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, ABM (POPCNT/LZCNT), and

AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...

Improvements over Bobcat

* Over 10% increase in clock frequency * Over 15% improvement in

instructions per clock In computer architecture, instructions per cycle (IPC), commonly called instructions per clock is one aspect of a processor's performance: the average number of instructions executed for each clock cycle. It is the multiplicative inverse of cycl ...

(IPC) * Added support for SSE4.1, SSE4.2, AES, CLMUL, MOVBE, AVX, F16C, BMI1 * Up to four CPU cores *

L2 cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, whic ...

is shared between cores * FPU datapath width increased to 128-bit * Added hardware integer divider * Enhanced cache prefetchers * Doubled bandwidth of load-store units * C6 and CC6 low power states with lower entry and exit latency * Smaller, 3.1 mm² area per core * Integrated

(FCH) *

Video Coding Engine Video Code Engine (VCE, was earlier referred to as Video Coding Engine, Video Compression Engine or Video Codec Engine in official AMD documentation) is AMD's video encoding application-specific integrated circuit implementing the video codec H. ...

Features

Processors

Consoles

Desktop

SoCs SOCS (suppressor of cytokine signaling proteins) refers to a family of genes involved in inhibiting the JAK-STAT signaling pathway. Genes * CISH * SOCS1 * SOCS2 * SOCS3 * SOCS4 * SOCS5 * SOCS6 * SOCS7 Suppressor of cytokine signaling 7 is a ...

using

Socket AM1 Socket FS1b (rebranded as Socket AM1 ) is a socket designed by AMD, launched in April 2014 for desktop SoCs in the value segment. Socket AM1 is intended for a class of CPUs that contain both an integrated GPU and a chipset, essentially forming ...

Desktop/Mobile (28 nm)

Server

Opteron X1100-series "Kyoto" (28 nm)

Opteron X2100-series "Kyoto" (28 nm)

Embedded

Jaguar derivative and successor

In 2017 a derivative of the Jaguar microarchitecture was announced in the APU of

Microsoft Microsoft Corporation is an American multinational technology corporation producing computer software, consumer electronics, personal computers, and related services headquartered at the Microsoft Redmond campus located in Redmond, Washi ...

's Xbox One X (Project Scorpio) revision to the

. The Project Scorpio APU is described as a 'customized' derivative of the Jaguar microarchitecture, utilizing eight cores clocked at 2.3 GHz. The Puma successor to Jaguar was released in 2014 and targeting entry level notebooks and tablets.

References

{{Single-board computer AMD x86 microprocessors AMD microarchitectures X86 microarchitectures