Haswell is the codename for a

processor Processor may refer to: Computing Hardware * Processor (computing) **Central processing unit (CPU), the hardware within a computer that executes a program *** Microprocessor, a central processing unit contained on a single integrated circuit (I ...

microarchitecture developed by Intel as the "fourth-generation core" successor to the Ivy Bridge (which is a die shrink/

tick Ticks (order Ixodida) are parasitic arachnids that are part of the mite superorder Parasitiformes. Adult ticks are approximately 3 to 5 mm in length depending on age, sex, species, and "fullness". Ticks are external parasites, living by ...

of the Sandy Bridge microarchitecture). Intel officially announced CPUs based on this microarchitecture on June 4, 2013, at

Computex Taipei COMPUTEX Taipei, or Taipei International Information Technology Show (), is a computer expo held annually in Taipei, Taiwan. Since the early 2000s, it is one of the largest computer and technology trade shows in the world. The last COMPUTEX w ...

2013, while a working Haswell chip was demonstrated at the 2011

Intel Developer Forum The Intel Developer Forum (IDF) was a biannual gathering of technologists to discuss Intel products and products based on Intel products. The first IDF was held in 1997. To emphasize the importance of China, the Spring 2007 IDF was held in Beijin ...

. With Haswell, which uses a

22 nm The 22 nm node is the process step following 32 nm in CMOS MOSFET semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm ...

process, Intel also introduced low-power processors designed for convertible or "hybrid"

ultrabooks Ultrabook is a marketing term, originated and trademarked by Intel, for a category of high-end laptop computers. They were originally marketed as featuring ultra thin form factor and light weight design without compromising battery life or perf ...

, designated by the "U" suffix. Haswell CPUs are used in conjunction with the Intel 8 Series chipsets, Intel 9 Series chipsets, and Intel C220 series chipsets. At least one Haswell-based processor is still being sold as of 2022, the Pentium G3420.

Design

The Haswell architecture is specifically designed to optimize the power savings and performance benefits from the move to FinFET (non-planar, "3D") transistors on the improved 22 nm process node. Haswell has been launched in three major forms: * Desktop version (

LGA 1150 LGA 1150, also known as Socket H3, is a zero insertion force flip-chip land grid array (LGA) CPU socket designed by Intel for CPUs built on the Haswell microarchitecture. This socket is also used by the Haswell's successor, Broad ...

socket and the

LGA 2011-v3 LGA 2011, also called ''Socket R'', is a CPU socket by Intel released on November 14, 2011. It launched along with LGA 1356 to replace its predecessor, LGA 1366 (Socket B) and LGA 1567. While LGA 1356 was designed for dual-processor or ...

socket): ''Haswell-DT'' * Mobile/Laptop version ( PGA socket): ''Haswell-MB'' * BGA version: ** 47 W and 57 W TDP classes: ''Haswell-H'' (for "All-in-one" systems, Mini-ITX form factor motherboards, and other small footprint formats) ** 13.5 W and 15 W TDP classes ( MCP): ''Haswell-ULT'' (for Intel's UltraBook platform) ** 10 W TDP class (SoC): ''Haswell-ULX'' (for tablets and certain UltraBook-class implementations)

Notes

* ULT = ''Ultra Low TDP''; ULX = ''Ultra Low eXtreme'' TDP * Only certain quad-core variants and BGA R-series

stock keeping unit In inventory management, a stock keeping unit (abbreviated as SKU and pronounced or ) is the unit of measure in which the stocks of a material are managed. Or to put it another way; is a distinct type of item for sale, purchased, or tracked in ...

s (SKUs) receive GT3e ( Intel Iris Pro 5200) integrated graphics. All other models have GT3 ( Intel HD 5000 or

Intel Iris Intel Graphics Technology (GT) is the collective name for a series of integrated graphics processors (IGPs) produced by Intel that are manufactured on the same package or die as the central processing unit (CPU). It was first introduced in 201 ...

5100), GT2 (Intel HD 4200, 4400, 4600, P4600 or P4700) or GT1 (Intel HD Graphics) integrated graphics. See also

Intel HD and Iris Graphics Intel Graphics Technology (GT) is the collective name for a series of integrated graphics processors (IGPs) produced by Intel that are manufactured on the same package or die as the central processing unit (CPU). It was first introduced in 201 ...

for more details. * Due to the low power requirements of tablet and UltraBook platforms, Haswell-ULT and Haswell-ULX are only available in dual-core configurations. All other versions come as dual- or quad-core variants.

Performance

Compared to Ivy Bridge: * Approximately 8% faster vector processing * Up to 5% higher single-threaded performance * 6% higher multi-threaded performance * Desktop variants of Haswell draw between 8% and 23% more power under load than Ivy Bridge. * A 6% increase in sequential CPU performance (eight execution ports per core versus six) * Up to 20% performance increase over the integrated HD4000 GPU (Haswell HD4600 vs Ivy Bridge's built-in Intel HD4000) * Total performance improvement on average is about 3% * Around 15 °C hotter than Ivy Bridge, while clock frequencies of over 4.6 GHz are achievable

Technology

Features carried over from Ivy Bridge

* 22 nm manufacturing process * 3D ''Tri-Gate'' FinFET transistors *

Micro-operation cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which ...

(Uop Cache) capable of storing 1.5 K

micro-operation In computer central processing units, micro-operations (also known as micro-ops or μops, historically also as micro-actions) are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed m ...

s (approximately 6 KB in size) * 14- to 19-stage instruction pipeline, depending on the micro-operation cache hit or miss (an approach used in the even earlier Sandy Bridge microarchitecture) *Improve OoO window from 168 to 192 *Queue Allocation from 28/threads to 56 * Mainstream variants are up to quad-core. * Native support for

dual-channel In the fields of digital electronics and computer hardware, multi-channel memory architecture is a technology that increases the data transfer rate between the DRAM memory and the memory controller by adding more channels of communication between ...

DDR3/DDR3L memory, with up to 32 GB of RAM on LGA 1150 variants * 64 KB (32 KB Instruction + 32 KB Data) L1 cache and 256 KB L2 cache per core * A total of 16 PCI Express 3.0 lanes on LGA 1150 variants

New features

CPU

* Wider core: fourth

arithmetic logic unit In computing, an arithmetic logic unit (ALU) is a combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to a floating-point unit (FPU), which operates on floating point nu ...

(ALU), third address generation unit (AGU), second branch execution unit (BEU), deeper buffers, higher cache bandwidth, improved front-end and memory controller, higher load/store bandwidth. * New instructions (HNI, includes

Advanced Vector Extensions 2 Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge ...

(AVX2),

gather Gather, gatherer, or gathering may refer to: Anthropology and sociology *Hunter-gatherer, a person or a society whose subsistence depends on hunting and gathering of wild foods *Intensive gathering, the practice of cultivating wild plants as a st ...

, BMI1, BMI2, ABM and

FMA3 The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations."FMA3 and FMA4 are not instruction sets, they are indi ...

support). * The instruction decode queue, which holds instructions after they have been decoded, is no longer statically partitioned between the two threads that each core can service. * Intel Transactional Synchronization Extensions (TSX) for the Haswell-EX variant. In August 2014 Intel announced that a bug exists in the TSX implementation on the current steppings of Haswell, Haswell-E, Haswell-EP and early Broadwell CPUs, which resulted in disabling the TSX feature on affected CPUs via a

microcode In processor design, microcode (μcode) is a technique that interposes a layer of computer organization between the central processing unit (CPU) hardware and the programmer-visible instruction set architecture of a computer. Microcode is a lay ...

update. *

Fully integrated voltage regulator A voltage regulator module (VRM), sometimes called processor power module (PPM), is a buck converter that provides microprocessor and chipset the appropriate supply voltage, converting , or to lower voltages required by the devices, allowing dev ...

(FIVR), thereby moving some of the components from motherboard onto the CPU. * New advanced power-saving system; due to Haswell's new low-power C6 and C7 sleep states, not all power supply units (PSUs) are suitable for computers with Haswell CPUs. * 37, 47, 57 W thermal design power (TDP) mobile processors. * 35, 45, 65, 84, 88, 95 and 130–140 W (high-end, Haswell-E) TDP desktop processors. * 15 W or 11.5W TDP processors for the Ultrabook platform (multi-chip package like Westmere) leading to reduced heat, which results in thinner as well as lighter Ultrabooks, but the performance level is slightly lower than the 17 W version. :

GPU

* Hardware graphics support for Direct3D 11.1 and

OpenGL OpenGL (Open Graphics Library) is a cross-language, cross-platform application programming interface (API) for rendering 2D and 3D vector graphics. The API is typically used to interact with a graphics processing unit (GPU), to achieve hardwa ...

4.3. Intel 10.18.14.5180 driver is the last planned driver release on Windows 7/8.1. * Four versions of the integrated GPU: GT1, GT2, GT3 and GT3e, where GT3 version has 40 execution units (EUs). Haswell's predecessor, Ivy Bridge, has a maximum of 16 EUs. GT3e version with 40 EUs and on-package 128 MB of embedded DRAM ( eDRAM), called Crystalwell, is available only in mobile H- SKUs and desktop ( BGA-only) R-SKUs. Effectively, this eDRAM is a Level 4 cache; it is shared dynamically between the on-die GPU and CPU, and serving as a

victim cache A victim cache is a small, usually fully associative cache placed in the refill path of a CPU cache that stores all the blocks evicted from that level of cache, originally proposed in 1990. In modern architectures, this function is typically perfor ...

to the CPU's Level 3 cache.

I/O

* New sockets and chipsets: ** LGA 1150 for desktops, and rPGA947 and BGA1364 for the mobile market. ** Z97 (performance) and H97 (mainstream)

chipset In a computer system, a chipset is a set of electronic components in one or more integrated circuits known as a "Data Flow Management System" that manages the data flow between the processor, memory and peripherals. It is usually found on the mo ...

s for the Haswell Refresh and Broadwell, in Q2 2014. **

with X99 chipset for the enthusiast-class desktop platform ''Haswell-E''. *

DDR4 Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth (" double data rate") interface. Released to the market in 2014, it is a variant of dynamic ran ...

for enterprise/server segments and for the Enthusiast-Class Desktop Platform Haswell-E * Variable Base clock (BClk) like LGA 2011. * Optional support for Thunderbolt technology and Thunderbolt 2.0 * Shrink of the

Platform Controller Hub The Platform Controller Hub (PCH) is a family of Intel's single-chip chipsets, first introduced in 2009. It is the successor to the Intel Hub Architecture, which used two chips - a northbridge and southbridge, and first appeared in the Intel 5 ...

(PCH), from 65 nm to

32 nm The 32 nm node is the step following the 45 nm process in CMOS (MOSFET) semiconductor device fabrication. "32-nanometre" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technology le ...

Server processors features

* Haswell-EP variant, released in September 2014, with up to 18 cores and marketed as the Xeon E5-1600 v3 and Xeon E5-2600 v3 series. * Haswell-EX variant, released in May 2015, with 18 cores and functioning TSX. * A new

cache Cache, caching, or caché may refer to: Places United States * Cache, Idaho, an unincorporated community * Cache, Illinois, an unincorporated community * Cache, Oklahoma, a city in Comanche County * Cache, Utah, Cache County, Utah * Cache Count ...

design. * Up to 35 MB total unified cache ( last level cache, LLC) for Haswell-EP and up to 40 MB for Haswell-EX. *

socket replaces LGA 2011 for the Haswell EP; the new socket has the same number of pins, but it is keyed differently due to electrical incompatibility. * The already launched Xeon E3 v3 Haswells will get a refresh in spring 2014, together with a refreshed Intel C220 series PCH chipset. * TDP up to 160 W for Haswell-EP. * Haswell-EP models with ten and more cores support ''cluster on die'' (COD) operation mode, allowing CPU's multiple columns of cores and last level cache (LLC) slices to be logically divided into what is presented as two non-uniform memory access (NUMA) CPUs to the operating system. By keeping data and instructions local to the "partition" of CPU which is processing them, therefore decreasing the LLC access latency, COD brings performance improvements to NUMA-aware operating systems and applications.

Haswell Refresh

Around the middle of 2014, Intel released a refresh of Haswell, simply titled ''Haswell Refresh''. When compared to the original Haswell CPUs lineup, Haswell Refresh CPUs offer a modest increase in clock frequencies, usually of 100 MHz. Haswell Refresh CPUs are supported by Intel's ''9 Series'' chipsets (Z97 and H97, codenamed Wildcat Point), while motherboards with ''8 Series'' chipsets (codenamed

Lynx Point The Platform Controller Hub (PCH) is a family of Intel's single-chip chipsets, first introduced in 2009. It is the successor to the Intel Hub Architecture, which used two chips - a northbridge and southbridge, and first appeared in the Intel 5 ...

) usually require a BIOS update to support Haswell Refresh CPUs. The CPUs codenamed ''Devil's Canyon'', covering the i5 and i7 K-series SKUs, employ a new and improved thermal interface material (TIM) called next-generation polymer thermal interface material (''NGPTIM''). This improved TIM reduces the CPU's operating temperatures and improves the overclocking potential, as something that had been problematic since the introduction of Ivy Bridge. Other changes for the Devil's Canyon CPUs include a TDP increase to 88 W, additional decoupling capacitors to help smooth out the outputs from the fully integrated voltage regulator (FIVR), and support for the VT-d that was previously limited to non-K-series SKUs. TSX was another feature brought over from the non-K-series SKUs, until August 2014 when a microcode update disabled TSX due to a bug that was discovered in its implementation.

Windows XP and Vista support

While Ivy Bridge is the last Intel processor to fully support all versions of Windows XP, Haswell includes limited driver support for certain XP editions such as POSReady2009. People have modified the graphics driver for these versions to adapt to normal Windows XP to varying degrees of success. Windows Vista support is also dropped with this processor as well. People who have installed x64 version of Vista have reported various problems such as services not starting automatically. The KB4493471 update (officially intended only for Windows Server 2008, but can be installed on Vista) contains a HAL driver that fixes most of these issues. Windows XP and earlier and x86 version of Vista is unaffected by this bug.

List of Haswell processors

Desktop processors

* All models support: ''

MMX MMX may refer to: * 2010, in Roman numerals Science and technology * MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel * MMX Mineração, a Brazilian mining company * Martian Moons eXploration, a Japane ...

, SSE, SSE2,

SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...

SSSE3 Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitectur ...

SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...

, SSE4.2, F16C, Enhanced Intel SpeedStep Technology (EIST),

Intel 64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...

, XD bit (an NX bit implementation), Intel VT-x,'' and ''

Smart Cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which ...

.'' ** Core i3, i5 and i7 support '' AVX, AVX2,

BMI1 Polycomb complex protein BMI-1 also known as polycomb group RING finger protein 4 (PCGF4) or RING finger protein 51 (RNF51) is a protein that in humans is encoded by the ''BMI1'' gene (B cell-specific Moloney murine leukemia virus integration ...

BMI2 Bit manipulation instructions sets (BMI sets) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD. The purpose of these instruction sets is to improve the speed of bit manipulation. All the instructions ...

,'' and ''

AES-NI An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard ...

.'' ** Core i3 and i7, as well as the Core i5-4570T and i5-4570TE, support '' Hyper-Threading (HT)''. ** Core i5 and i7 support ''

Turbo Boost Intel Turbo Boost is Intel's trade name for central processing units (CPUs) dynamic frequency scaling feature that automatically raises certain versions of its operating frequency when demanding tasks are running, thus enabling a higher resultin ...

2.0.'' ** Although it was initially supported on selected models, since August 2014 desktop variants no longer support '' TSX'' due to a bug that was discovered in its implementation; as a workaround, a microcode update disabled the TSX feature. ** SKUs below 45xx as well as R-series and K-series SKUs do not support '' Trusted Execution Technology'' or '' vPro.'' ** ''

Intel VT-d x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-a ...

'', which is Intel's IOMMU, is supported on all i5 and i7 SKUs except the i5-4670K and i7-4770K. Support for VT-d requires the chipset and motherboard to also support VT-d. ** Models i5-4690K and i7-4790K, codenamed Devil's Canyon, have a better internal

thermal grease Thermal paste (also called thermal compound, thermal grease, thermal interface material (TIM), thermal gel, heat paste, heat sink compound, heat sink paste or CPU grease) is a thermally conductive (but usually electrically insulating) chemi ...

to help heat escape and an improved internal voltage regulator ("FIVR"), to help deliver cleaner power in situations like overclocking. * Transistors: 1.4 billion * Die size: 177 mm² *

in following variants: ** R-series desktop processors feature Intel Iris Pro 5200 graphics (GT3e). ** All other currently known i3, i5 and i7 desktop processors include Intel HD 4600 graphics (GT2). ** The exceptions are processors 41xxx, which include HD 4400 graphics (GT2). ** Celeron and Pentium processors contain Intel HD Graphics (GT1). * Pentium G3258, also known as the ''Pentium Anniversary Edition'', has an unlocked multiplier. Its release marks 20 years of "Pentium" as a brand. The following table lists available desktop processors. : Some of these configurations could be disabled by the chipset. For example, H-series chipsets disable all PCIe 3.0 lane configurations except 1×16. : This feature also requires a chipset that supports VT-d like the Q87 chipset or the X99 chipset. : This is called ''20th Anniversary Edition'' and has an unlocked multiplier. SKU suffixes to denote: * K unlocked (adjustable CPU multiplier up to 63x) **The Pentium G3258 CPU is unlocked despite not having the K-suffix. * S performance-optimized lifestyle (low power with 65 W TDP) * T power-optimized lifestyle (ultra low power with 35–45 W TDP) * R BGA packaging / High-performance GPU (currently Iris Pro 5200 (GT3e)) * X extreme edition (adjustable CPU ratio with no ratio limit)

Server processors

* All models support: ''

, SSE, SSE2,

, SSE4.2, AVX (Advanced Vector Extensions), AVX2,

, F16C, BMI (Bit Manipulation Instructions 1)+BMI2, Enhanced Intel SpeedStep Technology (EIST),

, XD bit (an NX bit implementation), TXT,

Intel vPro Intel vPro technology is an umbrella marketing term used by Intel for a large collection of computer hardware technologies, including VT-x, VT-d, Trusted Execution Technology (TXT), and Intel Active Management Technology (AMT). When the vPro bra ...

, Intel VT-x,

, hyper-threading (except E3-1220 v3 and E3-1225 v3),

2.0,

'', and ''Smart Cache.'' * Haswell-EX models (E7-48xx/88xx v3) support '' TSX'', while for Haswell-E, Haswell-WS (E3-12xx v3) and Haswell-EP (E5-16xx/26xx v3) models it was disabled via a microcode update in August 2014, due to a bug that was discovered in the TSX implementation. * Transistors: 5.56 billion * Die size: 661 mm² The first digit of the model number designates the largest supported multi-socket configuration; thus, E5-26xx v3 models support up to dual-socket configurations, while the E7-48xx v3 and E7-88xx v3 models support up to quad- and eight-socket configurations, respectively. Also, E5-16xx/26xx v3 and E7-48xx/88xx v3 models have no integrated GPU. Lists of launched server processors are below, split between Haswell E3-12xx v3, E5-16xx/26xx v3 and E7-48xx/88xx v3 models. SKU suffixes to denote: * L low power

Mobile processors

* All models support: ''

, SSE, SSE2,

, SSE4.2, F16C, Enhanced Intel SpeedStep Technology (EIST), Intel VT-x,

, XD bit (an NX bit implementation)'', and ''Smart Cache.'' ** Core i3, i5 and i7 support '' AVX, AVX2, BMI1, BMI2,

'', and '' hyper-threading (HT)''. ** Core i3, i5 and i7 except the Core i3-4000M support ''

''. ** Core i5 and i7 except the Core i5-4410E, i5-4402EC, i7-4700EC, and i7-4702EC support ''

2.0.'' * Platform Controller Hub (PCH) integrated into the CPU package, slightly reducing the amount of space used on motherboards. * Transistors: 1.3 billion * Die size: 181 mm² The following table lists available mobile processors.

When a cooler or quieter mode of operation is desired, this mode specifies a lower TDP and lower guaranteed frequency versus the nominal mode.
This is the processor's rated frequency and TDP.
When extra cooling is available, this mode specifies a higher TDP and higher guaranteed frequency versus the nominal mode.

SKU suffixes to denote: * M mobile processor ( Socket G3) * Q quad-core * U ultra-low power (BGA1168 packaging) * X "extreme" * Y extreme low-power (BGA1168 packaging) * E / H BGA1364 packaging

Notes

References

External links

* * * * * * {{DEFAULTSORT:Haswell (microarchitecture) Haswell microarchitecture Intel microarchitectures Transactional memory X86 microarchitectures