Field Programmable Nanowire Interconnect (often abbreviated FPNI) is a new computer architecture developed by

Hewlett-Packard The Hewlett-Packard Company, commonly shortened to Hewlett-Packard ( ) or HP, was an American multinational information technology company headquartered in Palo Alto, California. HP developed and provided a wide variety of hardware components ...

. This is a defect-tolerant architecture, using the results of the

Teramac The ''Teramac'' was an experimental massively parallel computer designed by HP in the 1990s. The name reflected the project's vision to provide a programmable gate array system with capacity for a million gates running at a megahertz. Contrary to ...

experiment.

Technology

The design combines a nanoscale crossbar switch structure with conventional CMOS to create a hybrid chip that is simpler to fabricate and offers greater flexibility in the choice of nanoscale devices. The FPNI improves on a

field-programmable gate array A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence the term '' field-programmable''. The FPGA configuration is generally specified using a hardware d ...

(FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit – while providing up to eight times the density at less cost. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend

Moore's Law Moore's law is the observation that the number of transistors in a dense integrated circuit (IC) doubles about every two years. Moore's law is an observation and projection of a historical trend. Rather than a law of physics, it is an empir ...

without having to shrink the transistors.

References

External links

* http://www.iop.org/EJ/abstract/0957-4484/18/3/035204 Nanotechnology journal, Issue 3 (24 January 2007)Nano/CMOS architectures using a field-programmable nanowire interconnect Gate arrays {{comp-eng-stub