Within

digital electronics Digital electronics is a field of electronics involving the study of digital signals and the engineering of devices that use or produce them. It deals with the relationship between Binary number, binary inputs and outputs by passing electrical s ...

, the DIMS (delay-insensitive minterm synthesis) systemD. E. Muller, “Asynchronous logics and application to information processing,” Proc. Symp. Application of Switching Theory in Space Technology, H. Aiken and W. F. Main, Ed. , pp. 289-297, 1963. is an asynchronous design methodology making the least possible timing assumptions. Assuming only the

quasi-delay-insensitive A quasi-delay-insensitive circuit (QDI circuit) is an Asynchronous circuit, asynchronous circuit design methodology employed in Digital logic, digital logic design. Developed in response to the performance challenges of building Submicroscopic, su ...

delay model the generated designs need little if any timing hazard testing. The basis for DIMS is the use of two wires to represent each bit of data. This is known as a dual-rail data encoding. Parts of the system communicate using the early four-phase asynchronous protocol. The construction of DIMS logic gates comprises generating every possible minterm using a row of

C-element In Logic gate, digital computing, the Muller C-element (C-gate, hysteresis flip-flop, coincident flip-flop, or two-hand safety circuit) is a small binary sequential logic, logic circuit widely used in design of asynchronous circuits and systems. ...

s and then gathering the outputs of these using

OR gate The OR gate is a digital logic gate that implements logical disjunction. The OR gate outputs "true" if any of its inputs is "true"; otherwise it outputs "false". The input and output states are normally represented by different voltage levels. ...

s which generate the true and false output signals. With two dual-rail inputs the gate would be composed of four two-input C-elements. A three input gate uses eight three-input C-elements. Latches are constructed using two C-elements to store the data and an OR gate to acknowledge the input once the data has been latched by attaching as its inputs the data output wires. The acknowledge from the forward stage is inverted and passed to the C-elements to allow them to reset once the computation has completed. This latch design is known as the 'half latch'. Other asynchronous latches provide a higher data capacity and levels of decoupling. DIMS designs are large and slow but they have the advantage of being very robust.

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