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The AMD Bulldozer Family 15h is a microprocessor microarchitecture for the FX and Opteron line of processors, developed by
AMD Advanced Micro Devices, Inc. (AMD) is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. While it initially manufact ...
for the desktop and server markets. Bulldozer is the codename for this family of microarchitectures. It was released on October 12, 2011, as the successor to the K10 microarchitecture. Bulldozer is designed from scratch, not a development of earlier processors. The core is specifically aimed at computing products with TDPs of 10 to 125  watts. AMD claims dramatic performance-per-watt efficiency improvements in high-performance computing (HPC) applications with Bulldozer cores. The ''Bulldozer'' cores support most of the instruction sets implemented by Intel processors ( Sandy Bridge) available at its introduction (including
SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, SSE4.2, AES, CLMUL, and AVX) as well as new instruction sets proposed by AMD;
ABM ABM or Abm may refer to: Companies * ABM Industries, a US facility management provider * ABM Intelligence, a UK software company * Advantage Business Media, a US digital marketing and information services company * Associated British Maltsters, ...
, XOP,
FMA4 The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations."FMA3 and FMA4 are not instruction sets, they are ...
and F16C. Only Bulldozer GEN4 (
Excavator Excavators are heavy construction equipment consisting of a boom, dipper (or stick), bucket and cab on a rotating platform known as the "house". The house sits atop an undercarriage with tracks or wheels. They are a natural progression fro ...
) supports
AVX2 Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bri ...
instruction sets.


Overview

According to AMD, Bulldozer-based CPUs are based on GlobalFoundries' 32 nm Silicon on insulator (SOI) process technology and reuses the approach of DEC for multitasking computer performance with the arguments that it, according to press notes, "balances dedicated and shared computer resources to provide a highly compact, high units count design that is easily replicated on a chip for performance scaling." In other words, by eliminating some of the "redundant" elements that naturally creep into multicore designs, AMD has hoped to take better advantage of its hardware capabilities, while using less power. Bulldozer-based implementations built on
32nm The 32 nm node is the step following the 45 nm process in CMOS (MOSFET) semiconductor device fabrication. "32-nanometre" refers to the average half-pitch (i.e., half the distance between identical features) of a memory cell at this technology le ...
SOI with HKMG arrived in October 2011 for both servers and desktops. The server segment included the dual chip (16-core) Opteron processor codenamed ''Interlagos'' (for Socket G34) and single chip (4, 6 or 8 cores) ''Valencia'' (for
Socket C32 Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for low ...
), while the ''Zambezi'' (4, 6 and 8 cores) targeted desktops on Socket AM3+. Bulldozer is the first major redesign of AMD’s processor architecture since 2003, when the firm launched its K8 processors, and also features two 128-bit FMA-capable FPUs which can be combined into one 256-bit FPU. This design is accompanied by two integer clusters, each with 4 pipelines (the fetch/decode stage is shared). Bulldozer also introduced shared L2 cache in the new architecture. AMD calls this ''design'' a "Module". A 16-core processor design would feature eight of these "modules", but the operating system will recognize each "module" as two logical cores. The modular architecture consists of multithreaded shared L2 cache and FlexFPU, which uses simultaneous multithreading. Each physical integer core, two per module, is single threaded, in contrast with Intel's
Hyperthreading Hyper-threading (officially called Hyper-Threading Technology or HT Technology and abbreviated as HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multi ...
, where two virtual simultaneous threads share the resources of a single physical core. In a retrospective review, Jeremy Laird of APC magazine commented on Bulldozer issues, noted that it was slower than outgoing Phenom II K10 design, and that the PC software ecosystem had not yet "embraced" the multi-threaded model. By his observation, issues caused a big loss for AMD, that the company lost over 1 billion USD in 2012, and that some industry observers were predicting the bankruptcy by mid-2015. Company later managed to return to profit. Mentioned reasons for regaining the profitability were the earlier divesting of in-house manufacturing into GlobalFoundries and then outsourcing the manufacturing to
TSMC Taiwan Semiconductor Manufacturing Company Limited (TSMC; also called Taiwan Semiconductor) is a Taiwanese multinational semiconductor contract manufacturing and design company. It is the world's most valuable semiconductor company, the world' ...
and making a new
Ryzen Ryzen ( ) is a brand of multi-core x86-64 microprocessors designed and marketed by AMD for desktop, mobile, server, and embedded platforms based on the Zen microarchitecture. It consists of central processing units (CPUs) marketed for mainst ...
CPU design.


Architecture


Bulldozer core

Bulldozer made use of "Clustered Multithreading" (CMT), a technique where some parts of the processor are shared between two threads and some parts are unique for each thread. Prior examples of such an approach to unconventional multithreading can be traced way back to the 2005 Sun Microsystems' UltraSPARC T1 CPU. In terms of hardware complexity and functionality, a Bulldozer CMT module is equal to a dual-core processor in its integer calculation capabilities, and to either a single-core processor or a handicapped dual-core in terms of floating-point computational power, depending on whether the code is saturated in floating point instructions in both threads running on the same CMT module, and whether the FPU is performing 128-bit or 256-bit floating point operations. The reason for this is that for each two integer cores, that is, within the same module, there is a single floating-point unit consisting of a pair of 128-bit FMAC
execution unit In computer engineering, an execution unit (E-unit or EU) is a part of the central processing unit (CPU) that performs the operations and calculations as instructed by the computer program. It may have its own internal control sequence unit (not ...
s. CMT is in some way a simpler but similar design philosophy to SMT; both designs try to utilize execution units efficiently; in either method, when two threads compete for some execution pipelines, there is a loss in performance in one or more of the threads. Due to dedicated integer cores, the Bulldozer family modules performed roughly like a dual-core, dual-threaded processor during sections of code that were either wholly integer or a mix of integer and floating-point calculations; yet, due to the SMT use of the shared floating-point pipelines, the module would perform similarly to a single-core, dual-threaded SMT processor (SMT2) for a pair of threads saturated with floating-point instructions. (Both of these last two comparisons make the assumption that the processor possesses an equally wide and capable execution core, integer-wise and floating-point-wise, respectively.) Both CMT and SMT are at peak effectiveness while running integer and floating point code on a pair of threads. CMT stays at peak effectiveness while working on a pair of threads consisting both of integer code, while under SMT, one or both threads will underperform due to competition for integer execution units. The disadvantage for CMT is a greater number of idle integer execution units in a single threaded case. In the single threaded case, CMT is limited to use at most half of the integer execution units in its module, while SMT imposes no such limit. A large SMT core with integer circuitry as wide and fast as two CMT cores could in theory have momentarily up to twice an integer performance in a single thread case. (More realistically for general code as a whole, Pollack's Rule estimates a speedup factor of \sqrt, or approximately 40% increase in performance.) CMT processors and a typical SMT processor are similar in their efficient shared use of the L2 cache between a pair of threads. * A module consists of a coupling of two "conventional" x86 out of order processing cores. The processing core shares the early pipeline stages (e.g. L1i, fetch, decode), the FPUs, and the L2 cache with the rest of the module. ** Each module has the following independent hardware resources: ** 16 KB 4-way of L1d (way-predicted) per core and 2-way 64 KB of L1i per module, one way for each of the two cores ** 2 MB of L2 cache per module (shared between the two integer cores) **Write Coalescing Cache is a special cache that is part of L2 cache in Bulldozer microarchitecture. Stores from both L1D caches in the module go through the WCC, where they are buffered and coalesced. The WCC's task is reducing number of writes to the L2 cache. ** Two dedicated integer cores *** – ''each one includes two ALU and two
AGU Agu is an Igbo surname. People with the surname Agu * Agu Aarna (1915–1989), Estonian chemist * Agu Casmir (born 1984), Nigerian professional soccer player * Alloysius Agu (born 1967), Nigerian former football goalkeeper * Chiwetalu Agu ...
which are capable of a total of four independent arithmetic and memory operations per clock and per core'' *** – ''duplicating integer schedulers and execution pipelines offers dedicated hardware to each of two threads which double performance for multi-threaded integer loads'' *** – ''the second integer core in the module increases the Bulldozer module die by around 12%, which at chip level adds about 5% of total die space'' ** Two symmetrical 128-bit FMAC ( fused multiply–add capability) floating-point pipelines per module that can be unified into one large 256-bit-wide unit if one of the integer cores dispatches AVX instruction and two symmetrical x87/MMX/SSE capable FPPs for backward compatibility with SSE2 non-optimized software. Each FMAC unit is also capable of division and square root operations with variable latency. * All modules present share the L3 cache as well as an Advanced Dual-Channel Memory Sub-System (IMC – Integrated Memory Controller). * A module has 213 million transistors in an area of 30.9 mm² (including the 2 MB shared L2 cache) on an Orochi die. * The pipeline depth of Bulldozer (as well as Piledriver and Steamroller) is 20 cycles, compared to 12 cycles of the K10 core predecessor. The longer pipeline allowed the Bulldozer family of processors to achieve a much higher clock frequency compared to its K10 predecessors. While this increased frequencies and throughput, the longer pipeline also increased latencies and increased
branch misprediction In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow i ...
penalties. * The width of the Bulldozer integer core, four (2 ALU, 2 AGU), is somewhat less than the width of the K10 core, six (3 ALU, 3 AGU). Bobcat and Jaguar also used a four wide integer core, yet with lighter execution units: 1 ALU, 1 simple ALU, 1 load AGU, 1 store AGU. The issue widths (and peak instruction executions per cycle) of a Jaguar, K10, and Bulldozer core are 2, 3, and 4 respectively. This made Bulldozer a more superscalar design compared to Jaguar/Bobcat. However, due to K10's somewhat wider core (in addition to the lack of refinements and optimizations in a first generation design) the Bulldozer architecture typically performed with somewhat lower IPC compared to its K10 predecessors. It was not until the refinements made in Piledriver and Steamroller, that the IPC of the Bulldozer family distinctly began to exceed that of K10 processors such as Phenom II.


Branch predictor In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch (e.g., an if–then–else structure) will go before this is known definitively. The purpose of the branch predictor is to improve the flow i ...

*Two-level Branch Target Buffer(BTB) *Hybrid predictor for conditionals *Indirect predictor


Instruction set extensions

* Support for Intel's Advanced Vector Extensions ( AVX) instruction set, which supports 256-Bit floating point operations, and
SSE4.1 SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more ...
, SSE4.2, AES, CLMUL, as well as future 128-bit instruction sets proposed by AMD ( XOP,
FMA4 The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations."FMA3 and FMA4 are not instruction sets, they are ...
, and F16C), which have the same functionality as the
SSE5 The SSE5 (short for Streaming SIMD Extensions version 5) was a SIMD instruction set extension proposed by AMD on August 30, 2007 as a supplement to the 128-bit SSE core instructions in the AMD64 architecture. AMD chose not to implement SSE5 as ori ...
instruction set formerly proposed by AMD, but with compatibility to the AVX coding scheme. *Bulldozer GEN4 (
Excavator Excavators are heavy construction equipment consisting of a boom, dipper (or stick), bucket and cab on a rotating platform known as the "house". The house sits atop an undercarriage with tracks or wheels. They are a natural progression fro ...
) supports
AVX2 Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bri ...
instruction sets.


Process technology and clock frequency

* 11-metal layer 32 nm SOI process with implemented first generation GlobalFoundries's High-K Metal Gate (HKMG) * ''Turbo Core 2'' performance boost to increase clock frequency up to 500 MHz with all threads active (for most workloads) and up to 1 GHz with the half of the thread active, within the TDP limit. * The chip operates at 0.775 to 1.425 V, achieving clock frequencies of 3.6 GHz or more * Min-Max TDP: 25 – 140 watts


Cache and memory interface

* Up to 8 MB of L3 shared among all cores on the same silicon die (8 MB for 4 cores in Desktop segment and 16 MB for 8 cores in the Server segment), divided into four subcaches of 2 MB each, capable of operating at 2.2 GHz at 1.1125 V * Native
DDR3 Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed ...
memory support up to DDR3-1866 * Dual Channel DDR3 integrated memory controller for Desktop and Server/Workstation Opteron 42xx "Valencia"; Quad Channel DDR3 Integrated Memory Controller for Server/Workstation Opteron 62xx "Interlagos" * AMD claims support for two DIMMs of DDR3-1600 per channel. Two DIMMs of DDR3-1866 on a single channel will be down-clocked to 1600.


I/O and socket interface

*
HyperTransport HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low- latency point-to-point link that was introduced on April 2 ...
Technology rev. 3.1 (''3.20 GHz, 6.4 GT/s, 25.6 GB/s & 16-bit wide link'') "Magny-Cours"_on_the_socket_G34_Opteron_platform_in_March_2010_and_List_of_AMD_Opteron_microprocessors#Opteron_4100-series_"Lisbon"_(45_nm)_2.html" ;"title="List of AMD Opteron microprocessors#Opteron 6100-series "Magny-Cours" (45 nm)">"Magny-Cours" on the socket G34 Opteron platform in March 2010 and "Lisbon"_on_the_socket_C32_Opteron_platform_in_June_2010.html" ;"title="List of AMD Opteron microprocessors#Opteron 4100-series "Lisbon" (45 nm) 2">"Lisbon" on the socket C32 Opteron platform in June 2010">List of AMD Opteron microprocessors#Opteron 4100-series "Lisbon" (45 nm) 2">"Lisbon" on the socket C32 Opteron platform in June 2010* Socket AM3+ (''AM3r2'') ** 942-pin,
DDR3 Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed ...
support only ** Will retain backward compatibility with Socket AM3 motherboards (as per motherboard manufacturer choice and if BIOS updates are provided), however this not officially supported by AMD; AM3+ motherboards will be backward-compatible with AM3 processors. * For the server segment, the existing socket G34 (LGA1974) and
socket C32 Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for low ...
(LGA1207) will be used.


Features

CPU features table


Processors

The first revenue shipments of Bulldozer-based Opteron processors was announced on September 7, 2011. The FX-4100, FX-6100, FX-8120 and FX-8150 were released in October 2011; with remaining FX series AMD processors released at the end of the first quarter of 2012.


Desktop

Major Sources: CPU-World and Xbit-Labs


Server

There are two series of Bulldozer-based processors for servers: Opteron 4200 series (
Socket C32 Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for low ...
, code named Valencia, with up to four modules) and Opteron 6200 series ( Socket G34, code named Interlagos, with up to 8 modules).


False advertising lawsuit

In November 2015, AMD was sued under the
California Consumers Legal Remedies Act The California Consumers Legal Remedies Act ("CLRA") is the name for California Civil Code §§ 1750 et seq. The CLRA declare unlawful several "methods of competition and unfair or deceptive acts or practices undertaken by any person in a transacti ...
and Unfair Competition Law for allegedly misrepresenting the specifications of Bulldozer chips. The class-action lawsuit, filed on 26 October in the US District Court for the Northern District of California, claims that each Bulldozer module is in fact a single CPU core with a few dual-core traits, rather than a true dual-core design. In August 2019, AMD agreed to settle the suit for $12.1M.


Performance


Performance on Linux

On 24 October 2011, the first generation tests done by Phoronix confirmed that the performance of Bulldozer CPU was somewhat less than expected. In several tests, the CPU performed similarly to the older generation Phenom 1060T. The performance later substantially increased, as various compiler optimizations and CPU driver fixes were released.


Performance on Windows

The first Bulldozer CPUs were met with a mixed response. It was discovered that the FX-8150 performed poorly in benchmarks that were not highly threaded, falling behind the second-generation Intel Core i* series processors and being matched or even outperformed by AMD's own Phenom II X6 at lower clock speeds. In highly threaded benchmarks, the FX-8150 performed on par with the Phenom II X6, and the Intel Core i7 2600K, depending on the benchmark. Given the overall more consistent performance of the Intel Core i5 2500K at a lower price, these results left many reviewers underwhelmed. The processor was found to be extremely power-hungry under load, especially when overclocked, compared to Intel's Sandy Bridge. On 13 October 2011, AMD stated on its blog that "there are some in our community who feel the product performance did not meet their expectations", but showed benchmarks on actual applications where it outperformed the Sandy Bridge i7 2600k and AMD X6 1100T. In January 2012, Microsoft released two hotfixes for Windows 7 and Server 2008 R2 that marginally improve the performance of Bulldozer CPUs by addressing the thread scheduling concerns raised after the release of Bulldozer. On 6 March 2012, AMD posted a knowledge base article stating that there was a compatibility problem with FX processors, and certain games on the widely used digital game distribution platform, Steam. AMD stated that they had provided a
BIOS In computing, BIOS (, ; Basic Input/Output System, also known as the System BIOS, ROM BIOS, BIOS ROM or PC BIOS) is firmware used to provide runtime services for operating systems and programs and to perform hardware initialization during the b ...
update to several motherboard manufacturers (namely: Asus,
Gigabyte Technology Gigabyte Technology (branded as GIGABYTE or sometimes GIGA-BYTE; formally GIGA-BYTE Technology Co., Ltd.) is a Taiwanese manufacturer and distributor of computer hardware. Gigabyte's principal business is motherboards. It shipped 4.8 million moth ...
, MSI, and
ASRock ASRock Inc. is a Taiwanese manufacturer of motherboards, industrial PCs and home theater PCs (HTPC). Founded by Ted Hsu, it was founded in 2002 and is currently owned by Taiwanese electronics company Pegatron. History ASRock was originally spu ...
) that would fix the problem. In September 2014, AMD CEO Rory Read conceded the Bulldozer design had not been a "game-changing part", and that AMD had to live with the design for four years.


Overclocking

On 31 August 2011, AMD and a group of well-known overclockers including Brian McLachlan, Sami Mäkinen, Aaron Schradin, and Simon Solotko managed to set a new world record for CPU frequency using the unreleased and overclocked FX-8150 Bulldozer processor. Before that day, the record sat at 8.309 GHz, but the Bulldozer combined with liquid helium
cooling Cooling is removal of heat, usually resulting in a lower temperature and/or phase change. Temperature lowering achieved by any other means may also be called cooling.ASHRAE Terminology, https://www.ashrae.org/technical-resources/free-resources/a ...
reached a new high of 8.429 GHz. The record has since been overtaken at 8.58 GHz by Andre Yang using
liquid nitrogen Liquid nitrogen—LN2—is nitrogen in a liquid state at low temperature. Liquid nitrogen has a boiling point of about . It is produced industrially by fractional distillation of liquid air. It is a colorless, low viscosity liquid that is wide ...
. On August 22, 2014 and using an FX-8370 (Piledriver), The Stilt from Team Finland achieved a maximum CPU frequency of 8.722 GHz. The CPU clock frequency records set by overclocked Bulldozer CPUs were only broken almost a decade later by overclocks of Intel's 13th generation Core
Raptor Lake Raptor Lake is Intel's codename for the 13th-generation of Intel Core processors based on a hybrid architecture, utilizing Raptor Cove performance cores and Gracemont efficient cores. Raptor Lake launched on October 20, 2022. Mobile version ...
CPUs in October 2022.


Revisions

'' Piledriver'' is the AMD codename for its improved second-generation microarchitecture based on ''Bulldozer''. AMD ''Piledriver'' cores are found in
Socket FM2 Socket FM2 is a CPU socket used by AMD's desktop ''Trinity'' and ''Richland'' APUs to connect to the motherboard as well as Athlon X2 and Athlon X4 processors based on them. FM2 was launched on September 27, 2012. Motherboards which fe ...
''Trinity'' and ''Richland'' based series of APUs and CPUs and the Socket AM3+ ''Vishera'' based FX-series of CPUs. Piledriver was the last generation in the Bulldozer family to be available for socket AM3+ and to be available with an L3 cache. The Piledriver processors available for FM2 (and its mobile variant) sockets did not come with a L3 cache, as the L2 cache is the last-level cache for all FM2/FM2+ processors. '' Steamroller'' is the AMD codename for its third-generation microarchitecture based on an improved version of ''Piledriver''. ''Steamroller'' cores are found in the
Socket FM2+ Socket FM2+ (FM2b, FM2r2) is a zero insertion force CPU socket designed by AMD for their desktop "Kaveri" APUs (Steamroller-based) and Godavari APUs (Steamroller-based) to connect to the motherboard. The FM2+ has a slightly different pin configur ...
''Kaveri'' based series of APUs and CPUs. ''
Excavator Excavators are heavy construction equipment consisting of a boom, dipper (or stick), bucket and cab on a rotating platform known as the "house". The house sits atop an undercarriage with tracks or wheels. They are a natural progression fro ...
'' is the codename for the fourth-generation ''Bulldozer'' core. ''Excavator'' was implemented as 'Carrizo' A-series APUs, "Bristol Ridge" A-series APUs, and Athlon x4 CPUs.


See also

*
List of AMD CPU microarchitectures The following is a list of AMD CPU microarchitectures. Nomenclature Historically, AMD's CPU families were given a "K-number" (which originally stood for Kryptonite, an allusion to the Superman comic book character's fatal weakness) starting with ...
*
List of AMD FX microprocessors AMD FX is a series of AMD microprocessors for personal computers. The following is a list of AMD FX brand microprocessors. Some APUs also carry an FX model name, but the term "FX" normally only refers to CPUs which are not just APUs with the iGP ...
* Charles R. Moore (computer engineer) *
Alpha 21264 The Alpha 21264 is a Digital Equipment Corporation RISC microprocessor launched on 19 October 1998. The 21264 implemented the Alpha instruction set architecture (ISA). Description The Alpha 21264 is a four-issue superscalar microprocessor with o ...
* K10 (microarchitecture) *
Bobcat (microarchitecture) The AMD Bobcat Family 14h is a microarchitecture created by AMD for its AMD APUs, aimed at a low-power/low-cost market. It was revealed during a speech from AMD executive vice-president Henri Richard in Computex 2007 and was put into production ...
* Opteron *
Piledriver (microarchitecture) AMD Piledriver Family 15h is a microarchitecture developed by AMD as the second-generation successor to Bulldozer. It targets desktop, mobile and server markets. It is used for the AMD Accelerated Processing Unit (formerly Fusion), AMD FX, and the ...
* Steamroller (microarchitecture) * Excavator (microarchitecture) *
Zen (microarchitecture) Zen is the codename for a family of computer processor microarchitectures from AMD, first launched in February 2017 with the first generation of its Ryzen CPUs. It is used in Ryzen (desktop and mobile), Ryzen Threadripper (workstation/high end ...


References


External links


www.amd.com/en-us/products/processors/desktop/fx
{{DEFAULTSORT:Bulldozer (Processor) AMD x86 microprocessors AMD microarchitectures X86 microarchitectures