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Cannon Lake (formerly Skymont) is Intel's codename for the
10 nm The following are examples of orders of magnitude for different lengths. __TOC__ Overview Detailed list To help compare different orders of magnitude, the following list describes various lengths between 1.6 \times 10^ metres and 10^ ...
die shrink The term die shrink (sometimes optical shrink or process shrink) refers to the scaling of metal-oxide-semiconductor (MOS) devices. The act of shrinking a die is to create a somewhat identical circuit using a more advanced fabrication process, ...
of the
Kaby Lake Kaby Lake is Intel's codename for its seventh generation Core microprocessor family announced on August 30, 2016. Like the preceding Skylake, Kaby Lake is produced using a 14 nanometer manufacturing process technology. Breaking with Intel's ...
microarchitecture. As a die shrink, Cannon Lake is a new ''process'' in Intel's process-architecture-optimization execution plan as the next step in semiconductor fabrication. Cannon Lake CPUs are the first mainstream CPUs to include the
AVX-512 AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and implemented in Intel's Xeon Phi x200 (Knights Landing) and Skylake-X CPUs; t ...
instruction set. Prior to Cannon Lake's launch, Intel launched another 14 nm process refinement with the codename
Coffee Lake Coffee Lake is Intel's codename for its eighth generation Core microprocessor family, announced on September 25, 2017. It is manufactured using Intel's second 14 nm process node refinement. Desktop Coffee Lake processors introduced i5 and ...
. The successor of Cannon Lake is Ice Lake, powered by the Sunny Cove microarchitecture, which represents the ''architecture'' phase in the ''process-architecture-optimization'' model.


Design history and features

Cannon Lake was initially expected to be released in 2015/2016, but the release was pushed back to 2018. Intel demonstrated a laptop with an unknown Cannon Lake CPU at CES 2017 and announced that Cannon Lake based products would be available in 2018 at the earliest. At
CES 2018 CES (; formerly an initialism for Consumer Electronics Show) is an annual trade show organized by the Consumer Technology Association (CTA). Held in January at the Las Vegas Convention Center in Winchester, Nevada, United States, the event t ...
Intel announced that it had started shipping mobile Cannon Lake CPUs at the end of 2017 and would ramp up production in 2018. On April 26, 2018 in its report on first-quarter 2018 financial results, Intel stated it was currently shipping low-volume 10 nm product and expects 10 nm volume production to shift to 2019. In July 2018, Intel announced that volume production of Cannon Lake would be delayed yet again, to late Q2 2019. The first laptop featuring a Cannon Lake CPU, namely Intel Core i3-8121U, a dual core CPU with Hyper-Threading and Turbo Boost but without an integrated GPU, was released in May 2018 in very limited quantities. On August 16, 2018 Intel announced two new models of NUCs would use the 10 nm Cannon Lake-U i3-8121U CPU. These models later became more readily available at retail in late November 2018. On October 28, 2019, Intel announced that it will be discontinuing the i3-8121U and the Cannon Lake-powered Crimson Canyon NUC, with orders being taken till December 27, and shipping till February 28, 2020, making Cannon Lake not only one of the shortest-lived microarchitectures of Intel, but also the shortest-lived 10 nm x86 CPU microarchitecture (with only one CPU model to be released and manufactured for 1.5 years). In July 2021, Intel announced it would be removing support for Cannon Lake graphics in their Linux kernel driver, effective as of Linux 5.15, as no production Cannon Lake CPUs were shipped with graphics enabled; this removal resulted in a reduction of approximately 1,600 lines of code.


Improvements

* Intel Palm Cove CPU cores **
AVX-512 AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and implemented in Intel's Xeon Phi x200 (Knights Landing) and Skylake-X CPUs; t ...
instruction set extension * Intel's first 10 nm process technology


Products


Mobile processors


Cannon Lake-U


See also

*
List of Intel CPU microarchitectures The following is a ''partial'' list of Intel CPU microarchitectures. The list is ''incomplete''. Additional details can be found in Intel's Tick–tock model and Process–architecture–optimization model. x86 microarchitectures 16-bit ; ...


References

{{IntelProcessorRoadmap Intel products Intel microarchitectures Transactional memory