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A status register, flag register, or condition code register (CCR) is a collection of status
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bits for a processor. Examples of such registers include FLAGS register in the
x86 architecture x86 (also known as 80x86 or the 8086 family) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel, based on the 8086 microprocessor and its 8-bit-external-bus variant, the 8088. T ...
, flags in the
program status word The program status word (PSW) is a register that performs the function of a status register and program counter, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the IBM System/3 ...
(PSW) register in the IBM System/360 architecture through
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, and the application program status register (APSR) in the ARM Cortex-A architecture. The status register is a hardware register that contains information about the state of the processor. Individual bits are implicitly or explicitly read and/or written by the
machine code In computer programming, machine code is computer code consisting of machine language instructions, which are used to control a computer's central processing unit (CPU). For conventional binary computers, machine code is the binaryOn nonb ...
instructions executing on the processor. The status register lets an instruction take action contingent on the outcome of a previous instruction. Typically, flags in the status register are modified as effects of arithmetic and bit manipulation operations. For example, a Z bit may be set if the result of the operation is zero and cleared if it is nonzero. Other classes of instructions may also modify the flags to indicate status. For example, a string instruction may do so to indicate whether the instruction terminated because it found a match/mismatch or because it found the end of the string. The flags are read by a subsequent conditional instruction so that the specified action (depending on the processor, a jump, call, return, or so on) occurs only if the flags indicate a specified result of the earlier instruction. Some CPU architectures, such as the MIPS and
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, do not use a dedicated flag register. Others do not implicitly set and/or read flags. Such machines either do not pass ''implicit'' status information between instructions at all, or they pass it in an explicitly selected general purpose register. A status register may often have other fields as well, such as more specialized flags,
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enable bits, and similar types of information. During an interrupt, the status of the thread currently executing can be preserved (and later recalled) by storing the current value of the status register along with the
program counter The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 and Itanium microprocessors, and sometimes called the instruction address register (IAR), the instruction counter, or just part of the instruction sequencer, ...
and other active registers into the machine stack or some other reserved area of memory.


Common flags

This is a list of the most common CPU status register flags, implemented in almost all modern processors.


Other flags

On some processors, the status register also contains flags such as these:


CPU architectures without arithmetic flags

Status flags enable an instruction to act based on the result of a previous instruction. In pipelined processors, such as
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and speculative processors, this can create hazards that slow processing or require extra hardware to work around them. Some very long instruction word processors dispense with the status flags. A single instruction both performs a test and indicates on which outcome of that test to take an action, such as Compare ''a'' with ''b'' and Jump to ''c'' if Equal. The result of the test is not saved for subsequent instructions. Another alternative to the status register is for processor instructions to deposit status information in a general-purpose register when the program requests it. MIPS,
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, DEC Alpha, and
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are examples of architectures that provide comparison instructions that store the comparison result in a general-purpose register, as a single bit or a numeric value of 0 or 1. Conditional branches act based on the value in the general-purpose register. Usually, comparison instructions test equality or signed/unsigned magnitude. To test for other conditions, a program uses an equivalence formula. For example, MIPS has no "carry bit" but a program performing multiple-word addition can test whether a single-word addition of registers overflowed by testing whether the sum is lower than an operand: # alow = blow + clow addu alow, blow, clow # set tmp = 1 if alow < clow, else 0 sltu tmp, alow, clow addu ahigh, bhigh, chigh addu ahigh, ahigh, tmp The sltu instruction sets tmp to 1 or 0 based on the specified comparison of its two other operands. (Here, the general-purpose register tmp is not used as a status register to govern a conditional jump; rather, the possible value of 1, indicating carry from the low-order addition, is added to the high-order word.) This scheme becomes less convenient when adding three or more words, as there are two additions when computing b + c + tmp, either of which may generate a carry, which must be detected with two sltu instructions. Fortunately, those two carries may be added to each other without risk of overflow, so the situation stabilizes at five instructions per word added.


See also

* Control register * CPU flag (x86) *
Flag field A bit field is a data structure that maps to one or more adjacent bits which have been allocated for specific purposes, so that any single bit or group of bits within the structure can be set or inspected. A bit field is most commonly used to repr ...


References

{{DEFAULTSORT:Status Register Control flow Central processing unit Digital registers