In
electronics
The field of electronics is a branch of physics and electrical engineering that deals with the emission, behaviour and effects of electrons using electronic devices. Electronics uses active devices to control electron flow by amplification ...
and especially
synchronous digital circuits, a clock signal (historically also known as ''logic beat''
) oscillates between a high and a low state and is used like a
metronome to coordinate actions of digital
circuits.
A clock
signal is produced by a
clock generator. Although more complex arrangements are used, the most common clock signal is in the form of a
square wave
A square wave is a non-sinusoidal periodic waveform in which the amplitude alternates at a steady frequency between fixed minimum and maximum values, with the same duration at minimum and maximum. In an ideal square wave, the transitions b ...
with a 50%
duty cycle, usually with a fixed, constant frequency. Circuits using the clock signal for synchronization may become active at either the rising edge, falling edge, or, in the case of
double data rate, both in the rising and in the falling edges of the clock cycle.
Digital circuits
Most
integrated circuits (ICs) of sufficient complexity use a clock signal in order to synchronize different parts of the circuit, cycling at a rate slower than the worst-case internal
propagation delays. In some cases, more than one clock cycle is required to perform a predictable action. As ICs become more complex, the problem of supplying accurate and synchronized clocks to all the circuits becomes increasingly difficult. The preeminent example of such complex chips is the
microprocessor, the central component of modern computers, which relies on a clock from a
crystal oscillator. The only exceptions are
asynchronous circuits such as
asynchronous CPUs.
A clock signal might also be gated, that is, combined with a controlling signal that enables or disables the clock signal for a certain part of a circuit. This technique is often used to save power by effectively shutting down portions of a digital circuit when they are not in use, but comes at a cost of increased complexity in timing analysis.
Single-phase clock
Most modern
synchronous circuits use only a "single phase clock" – in other words, all clock signals are (effectively) transmitted on 1 wire.
Two-phase clock
In
synchronous circuits, a "two-phase clock" refers to clock signals distributed on 2 wires, each with non-overlapping pulses. Traditionally one wire is called "phase 1" or "φ1" (
phi1), the other wire carries the "phase 2" or "φ2" signal.
[Two-phase clock](_blank)
Because the two phases are guaranteed non-overlapping,
gated latches rather than
edge-triggered flip-flops can be used to store
state information so long as the inputs to latches on one phase only depend on outputs from latches on the other phase. Since a gated latch uses only four gates versus six gates for an edge-triggered flip-flop, a two phase clock can lead to a design with a smaller overall gate count but usually at some penalty in design difficulty and performance.
Metal oxide semiconductor (MOS) ICs typically used dual clock signals (a two-phase clock) in the 1970s. These were generated externally for both the
Motorola 6800 and
Intel 8080 microprocessors.
[ Motorola's Component Products Department sold hybrid ICs that included a quartz oscillator. These IC produced the two-phase non-overlapping waveforms the 6800 and 8080 required. Later Intel produced the 8224 clock generator and Motorola produced the MC6875. The Intel 8085 and the Motorola 6802 include this circuitry on the microprocessor chip.] The next generation of microprocessors incorporated the clock generation on chip. The 8080 uses a 2 MHz clock but the processing throughput is similar to the 1 MHz 6800. The 8080 requires more clock cycles to execute a processor instruction. The 6800 has a minimum clock rate of 100 kHz and the 8080 has a minimum clock rate of 500 kHz. Higher speed versions of both microprocessors were released by 1976.
The
6501 requires an external 2-phase clock generator.
The
MOS Technology 6502 uses the same 2-phase logic internally, but also includes a two-phase clock generator on-chip, so it only needs a single phase clock input, simplifying system design.
4-phase clock
Some early integrated circuits use
four-phase logic, requiring a four phase clock input consisting of four separate, non-overlapping clock signals.
This was particularly common among early microprocessors such as the
National Semiconductor IMP-16,
Texas Instruments TMS9900, and the
Western Digital WD16 chipset used in the DEC LSI-11.
Four phase clocks have only rarely been used in newer CMOS processors such as the DEC WRL MultiTitan microprocessor. and in
Intrinsity's Fast14 technology. Most modern microprocessors and
microcontroller
A microcontroller (MCU for ''microcontroller unit'', often also MC, UC, or μC) is a small computer on a single VLSI integrated circuit (IC) chip. A microcontroller contains one or more CPUs (processor cores) along with memory and programmable i ...
s use a single-phase clock.
Clock multiplier
Many modern
microcomputer
A microcomputer is a small, relatively inexpensive computer having a central processing unit (CPU) made out of a microprocessor. The computer also includes memory and input/output (I/O) circuitry together mounted on a printed circuit board (PC ...
s use a "
clock multiplier
In computing, the clock multiplier (or CPU multiplier or bus/core ratio) sets the ratio of an internal CPU clock rate to the externally supplied clock. A CPU with a 10x multiplier will thus see 10 internal cycles (produced by PLL-based frequency m ...
" which multiplies a lower frequency external clock to the appropriate
clock rate of the microprocessor. This allows the CPU to operate at a much higher frequency than the rest of the computer, which affords performance gains in situations where the CPU does not need to wait on an external factor (like memory or
input/output
In computing, input/output (I/O, or informally io or IO) is the communication between an information processing system, such as a computer, and the outside world, possibly a human or another information processing system. Inputs are the signals ...
).
Dynamic frequency change
The vast majority of digital devices do not require a clock at a fixed, constant frequency.
As long as the minimum and maximum clock periods are respected, the time between clock edges can vary widely from one edge to the next and back again.
Such digital devices work just as well with a clock generator that dynamically changes its frequency, such as
spread-spectrum clock generation,
dynamic frequency scaling, etc.
Devices that use
static logic do not even have a maximum clock period (or in other words, minimum clock frequency); such devices can be slowed and paused indefinitely, then resumed at full clock speed at any later time.
Other circuits
Some sensitive
mixed-signal circuits, such as precision
analog-to-digital converters, use
sine wave
A sine wave, sinusoidal wave, or just sinusoid is a curve, mathematical curve defined in terms of the ''sine'' trigonometric function, of which it is the graph of a function, graph. It is a type of continuous wave and also a Smoothness, smooth p ...
s rather than square waves as their clock signals, because square waves contain high-frequency
harmonics that can interfere with the analog circuitry and cause
noise. Such sine wave clocks are often
differential signals, because this type of signal has twice the
slew rate, and therefore half the timing uncertainty, of a
single-ended signal with the same voltage range. Differential signals radiate less strongly than a single line. Alternatively, a single line shielded by power and ground lines can be used.
In CMOS circuits, gate capacitances are charged and discharged continually. A capacitor does not dissipate energy, but energy is wasted in the driving transistors. In
reversible computing,
inductors can be used to store this energy and reduce the energy loss, but they tend to be quite large. Alternatively, using a sine wave clock, CMOS
transmission gates and energy-saving techniques, the power requirements can be reduced.
Distribution
The most effective way to get the clock signal to every part of a chip that needs it, with the lowest skew, is a metal grid. In a large microprocessor, the power used to drive the clock signal can be over 30% of the total power used by the entire chip. The whole structure with the gates at the ends and all amplifiers in between have to be loaded and unloaded every cycle.
To save energy,
clock gating temporarily shuts off part of the tree.
The clock distribution network (or clock tree, when this network forms a tree) distributes the clock signal(s) from a common point to all the elements that need it. Since this function is vital to the operation of a synchronous system, much attention has been given to the characteristics of these clock signals and the
electrical network
An electrical network is an interconnection of electrical components (e.g., batteries, resistors, inductors, capacitors, switches, transistors) or a model of such an interconnection, consisting of electrical elements (e.g., voltage sour ...
s used in their distribution. Clock signals are often regarded as simple control signals; however, these signals have some very special characteristics and attributes.
Clock signals are typically loaded with the greatest
fanout and operate at the highest speeds of any signal within the synchronous system. Since the data signals are provided with a temporal reference by the clock signals, the clock
waveforms must be particularly clean and sharp. Furthermore, these clock signals are particularly affected by technology scaling (see
Moore's law
Moore's law is the observation that the number of transistors in a dense integrated circuit (IC) doubles about every two years. Moore's law is an observation and projection of a historical trend. Rather than a law of physics, it is an empir ...
), in that long
global interconnect In integrated circuits (ICs), interconnects are structures that connect two or more circuit elements (such as transistors) together electrically. The design and layout of interconnects on an IC is vital to its proper function, performance, power eff ...
lines become significantly more resistive as line dimensions are decreased. This increased line resistance is one of the primary reasons for the increasing significance of clock distribution on synchronous performance. Finally, the control of any differences and uncertainty in the arrival times of
the clock signals can severely limit the maximum performance of the entire system and create catastrophic
race conditions in which an incorrect data signal may latch within a register.
Most synchronous ''
digital'' systems consist of cascaded banks of sequential
registers with
combinational logic between each set of registers. The
functional requirements of the digital system are satisfied by the logic stages. Each logic stage introduces delay that affects timing performance, and the timing performance of the digital design can be evaluated relative to the timing requirements by a timing analysis. Often special consideration must be made to meet the timing requirements. For example, the global performance and local timing requirements may be satisfied by
the careful insertion of
pipeline registers into equally spaced time windows to satisfy critical worst-case ''
timing constraints
Timing is the tracking or planning of the spacing of events in time. It may refer to:
* Timekeeping, the process of measuring the passage of time
* Synchronization
Synchronization is the coordination of events to operate a system in unis ...
''. The proper design of the clock distribution network helps ensure that critical timing requirements are satisfied and that no race conditions exist (see also
clock skew).
The delay components that make up a general synchronous system are composed of the following three individual subsystems: the memory storage elements, the logic elements, and the clocking circuitry and distribution network.
Novel structures are currently under development to ameliorate these issues and provide effective solutions. Important areas of research include resonant clocking techniques, on-chip optical interconnect, and local synchronization methodologies.
See also
References
Further reading
*
Eby G. Friedman (Ed.), ''Clock Distribution Networks in VLSI Circuits and Systems'', , IEEE Press. 1995.
*
Eby G. Friedman, , ''Proceedings of the IEEE'', Vol. 89, No. 5, pp. 665–692, May 2001.
"ISPD 2010 High Performance Clock Network Synthesis Contest" International Symposium on Physical Design, Intel, IBM, 2010.
* D.-J. Lee
"High-performance and Low-power Clock Network Synthesis in the Presence of Variation" Ph.D. dissertation, University of Michigan, 2011.
* I. L. Markov, D.-J. Lee
"Algorithmic Tuning of Clock Trees and Derived Non-Tree Structures" in Proc. Int'l. Conf. Comp.-Aided Design (ICCAD), 2011.
* V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic, and N. M. Nedovic, ''Digital System Clocking: High-Performance and Low-Power Aspects'', {{ISBN, 0-471-27447-X, IEEE Press/Wiley-Interscience, 2003.
* Mitch Dale
"The power of RTL Clock-gating" ''Electronic Systems Design Engineering Incorporating Chip Design'', January 20, 2007.
----
Adapted fro
Eby Friedmans column in the AC
SIGDA
b
Igor Markov
br />
Original text is available at https://web.archive.org/web/20100711135550/http://www.sigda.org/newsletter/2005/eNews_051201.html
Synchronization