Circuit underutilization also chip underutilization, programmable circuit underutilization, gate underutilization, logic block underutilization refers to a physical incomplete utility of
semiconductor grade silicon on a standardized mass-produced
circuit programmable chip, such as a
gate array
A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) using a semiconductor device fabrication, prefabricated chip with components that are later interconnected into logic devices (e.g. NAN ...
type
ASIC, an
FPGA, or a
CPLD.
Gate array
In the example of a
gate array
A gate array is an approach to the design and manufacture of application-specific integrated circuits (ASICs) using a semiconductor device fabrication, prefabricated chip with components that are later interconnected into logic devices (e.g. NAN ...
, which may come in sizes of 5,000 or 10,000 gates, a design which utilizes even 5,001 gates would be required to use a 10,000 gate chip. This inefficiency results in underutilization of the silicon.
FPGA
Due to the design components of field-programmable gate array into
logic blocks, simple designs that underutilize a single block suffer from gate underutilization, as do designs that overflow onto multiple blocks, such as designs that use wide gates.
Additionally, the very generic
architecture of FPGAs lends to high inefficiency;
multiplexers occupy silicon real estate for programmable selection, and an abundance of
flip-flops to reduce
setup and hold times, even if the design does not require them,
[ resulting in 40 times less density than of standard cell ASICs.
]
See also
* Circuit minimization
* Don't-care condition
References
*
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