Athlon II is a family of AMD multi-core 45 nm

central processing unit A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, a ...

s, which is aimed at the budget to mid-range market and is a complementary product lineup to the

Phenom II Phenom II is a family of AMD's multi-core 45 nm processors using the AMD K10 microarchitecture, succeeding the original Phenom. Advanced Micro Devices released the Socket AM2+ version of Phenom II in December 2008, while Socket AM3 version ...

Features

The Athlon II series is based on the

AMD K10 The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. Though there were once reports that the K10 had been canceled,

architecture and derived from the Phenom II series. However, unlike its Phenom siblings, it does not contain any

L3 Cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, wh ...

. There are two principal Athlon II dies: the dual-core Regor die with 1 MB L2 Cache per core and the four-core Propus with 512 KB per core. Regor is a native dual-core design with lower TDP and additional L2 to offset the removal of L3 cache. The Athlon II x2 200e-220 chips have less L2 cache than the rest of the Regor line. The triple-core ''Rana'' is derived from the Propus quad-core design, with one core disabled. In some cases, the Phenom II Deneb die is used with disabled L3 cache and cores in the case.Athlon II X2 220 unlocks into Phenom II 920
/ref> Includes: AMD Direct Connect Architecture AMD Wide Floating Point Accelerator AMD Digital Media XPress 2.0 Technology AMD PowerNow! Technology (Cool’n’Quiet Technology)

HyperTransport HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low- latency point-to-point link that was introduced on April 2 ...

Technology (not the same as Intel

Hyper-Threading Hyper-threading (officially called Hyper-Threading Technology or HT Technology and abbreviated as HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multipl ...

Technology) Processors with an "e" following the model number (e.g., 245e) are low-power models, typically 45W for Athlons, 65W for Phenoms. Processors with a "u" following the model number (e.g., 250u) are ultra-low voltage models. * For a list of Athlon II processors, see: List of AMD Athlon II processors

Features table

CPU features table

Cores

''Regor'' (45 nm SOI with immersion lithography)

* Two

AMD K10 The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. Though there were once reports that the K10 had been canceled,

cores (Some are chip harvested Propus or Deneb with two cores disabled) * L1 cache: 64 kB + 64 kB (

data In the pursuit of knowledge, data (; ) is a collection of discrete values that convey information, describing quantity, quality, fact, statistics, other basic units of meaning, or simply sequences of symbols that may be further interpret ...

+ instructions) per core * L2 cache: 1024 kB per core, full-speed (512 kB per core in Athlon II X2 200e-220) * Memory controller: dual channel DDR2-1066 MHz (AM2+), dual channel DDR3-1333 (AM3) with unganging option *

MMX MMX may refer to: * 2010, in Roman numerals Science and technology * MMX (instruction set), a single-instruction, multiple-data instruction set designed by Intel * MMX Mineração, a Brazilian mining company * Martian Moons eXploration, a Japane ...

, Extended

3DNow! 3DNow! is a deprecated extension to the x86 instruction set developed by Advanced Micro Devices (AMD). It adds single instruction multiple data (SIMD) instructions to the base x86 instruction set, enabling it to perform vector processing of fl ...

, SSE,

SSE2 SSE2 (Streaming SIMD Extensions 2) is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000. It extends the earlier SSE i ...

SSE3 SSE3, Streaming SIMD Extensions 3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 (x86) architecture. Intel introduced SSE3 in early 2004 with the Prescott revis ...

, SSE4a,

AMD64 x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging m ...

, Cool'n'Quiet,

NX bit The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is ...

AMD-V x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-as ...

Socket AM3 Socket AM3 is a CPU socket for Advanced Micro Devices, AMD Central processing unit, processors. AM3 was launched on February 9, 2009 as the successor to Socket AM2+, alongside the initial grouping of Phenom II processors designed for it. The sole ...

with 2 GHz * Die Size: 117 mm² * Power consumption ( TDP): 25-65 Watts * First release ** June 2009 (Stepping C2) * Clock rate: 1.6 - 3.6 GHz * Models: Athlon II X2 250u - 280

''Rana'' (45 nm SOI with immersion lithography)

* Three

AMD K10 The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. Though there were once reports that the K10 had been canceled,

cores chip harvested from Propus or Deneb with one core disabled * L1 cache: 64 kB + 64 kB (

+ instructions) per core * L2 cache: 512 kB per core, full-speed * Memory controller: dual channel DDR2-1066 MHz (AM2+), dual channel DDR3-1333 (AM3) with unganging option *

, Extended

, SSE,

, SSE4a,

, Cool'n'Quiet,

with 2 GHz * Die Size: 169 mm² * Power consumption (TDP): 45 Watts or 95 Watts * First release ** October 2009 (Stepping C2) * Clock rate: 2.2–3.4 GHz * Models: Athlon II X3 400e - 460

''Propus'' (45 nm SOI with immersion lithography)

* Four

AMD K10 The AMD Family 10h, or K10, is a microprocessor microarchitecture by AMD based on the K8 microarchitecture. Though there were once reports that the K10 had been canceled,

cores chip harvested from Deneb with L3 cache disabled * L1 cache: 64 kB + 64 kB (

+ instructions) per core * L2 cache: 512 kB per core, full-speed * Memory controller: dual channel DDR2-1066 MHz (AM2+), dual channel DDR3-1333 (AM3) with unganging option *

, Extended

, SSE,

, SSE4a,

, Cool'n'Quiet,

with 2 GHz * Die Size: 169 mm² * Power consumption (TDP): 45 Watts or 95 Watts * First release ** September 2009 (Stepping C2) * Clock rate: 2.2–3.1 GHz * Models: Athlon II X4 600e - 645
Phenom II x4 840

External links

AMD product website
{{DEFAULTSORT:Athlon Ii Advanced Micro Devices x86 microprocessors

Features

Features table

Cores

''Regor'' (45 nm SOI with immersion lithography)

''Rana'' (45 nm SOI with immersion lithography)

''Propus'' (45 nm SOI with immersion lithography)

See also

External links