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Alder Lake is Intel's
codename A code name, call sign or cryptonym is a code word or name used, sometimes clandestinely, to refer to another name, word, project, or person. Code names are often used for military purposes, or in espionage. They may also be used in industrial c ...
for the 12th generation of
Intel Core Intel Core is a line of streamlined midrange consumer, workstation and enthusiast computer central processing units (CPUs) marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors at the time o ...
processors based on a hybrid architecture utilizing
Golden Cove Golden Cove is a codename for a CPU microarchitecture developed by Intel and released in November 2021. It succeeds four microarchitectures: Sunny Cove, Skylake, Willow Cove, and Cypress Cove. It is fabricated using Intel's Intel 7 process no ...
performance cores and Gracemont efficient cores. It is fabricated using Intel's Intel 7 process, previously referred to as Intel 10 nm Enhanced SuperFin (10ESF). The 10ESF has a 10%-15% boost in performance over the 10SF used in the mobile Tiger Lake processors. Intel officially announced 12th Gen Intel Core CPUs on October 27, 2021. Intel officially announced 12th Gen Intel Core mobile CPUs and non-K series desktop CPUs on January 4, 2022. Intel officially announced the launch of Alder Lake-P and -U series on February 23, 2022, and Alder Lake-HX series on May 10, 2022.


History

Fabricated using Intel's Intel 7 process, which was previously referred to as Intel 10 nm Enhanced SuperFin (10ESF), Intel officially announced 12th Gen Intel Core CPUs on October 27, 2021. Intel then officially announced 12th Gen Intel Core mobile CPUs and non-K series desktop CPUs on January 4, 2022. It further was announced in January 2022 that Intel Alder Lake would use a hybrid architecture combining performance and efficiency cores, similar to big.LITTLE which had been created by the semiconductor firm
Arm In human anatomy, the arm refers to the upper limb in common usage, although academically the term specifically means the upper arm between the glenohumeral joint (shoulder joint) and the elbow joint. The distal part of the upper limb between th ...
in the United Kingdom. This was the second Intel's hybrid architecture, after the mobile-only Lakefield released in June 2020. While the desktop Alder Lake processors were already on the market by January 2022, the mobile processors were not, although release was expected early that year. Starting cost were USD $289 for the Core i5-12600K. Gracemont was the name given to the efficiency cores, while
Golden Cove Golden Cove is a codename for a CPU microarchitecture developed by Intel and released in November 2021. It succeeds four microarchitectures: Sunny Cove, Skylake, Willow Cove, and Cypress Cove. It is fabricated using Intel's Intel 7 process no ...
cores were set for tasks such as gaming and video processing. First laptop tests were performed later that month, with
PCMag ''PC Magazine'' (shortened as ''PCMag'') is an American computer magazine published by Ziff Davis. A print edition was published from 1982 to January 2009. Publication of online editions started in late 1994 and have continued to the present ...
positively reviewing the Core i9-12900HK, stating the H series represented "Intel's enthusiast line," with "the same hybrid designs" also in the P-series and U-series chips to come out later that year. In April 2022, press reported on "hints" that Intel was working on Alder Lake-X. Intel officially announced the HX processor series on May 10, 2022, including Core i5, Core i7 and Core i9 models, when Intel announced "seven new mobile processors for the 12th Gen Intel Core mobile family at its Intel Vision event. With the lineup based on Intel's desktop Alder Lake chips, it was named the Alder Lake-HX series, or 12th-gen Core HX, with the Core i9-12950HX as the flagship and Intel's first 16-core chip designed for laptops.


Features


CPU

* Golden Cove performance cores ("P-cores") ** Dedicated floating-point adders ** New 6-wide instruction decoder (from 4-wide in
Rocket Lake Rocket Lake is Intel's codename for its 11th generation Core microprocessors. Released on March 30, 2021, it is based on the new Cypress Cove microarchitecture, a variant of Sunny Cove (used by Intel's Ice Lake mobile processors) backporte ...
/ Tiger Lake) with the ability to fetch up to 32 bytes of instructions per cycle (from 16) ** 12 execution ports (from 10) ** 512 reorder-buffer entries (from 352) ** 6-wide μOP allocations (from 5) ** μOP cache size increased to 4K entries (up from 2.25K) ** AVX-VNNI, a VEX-coded variant of AVX512-VNNI for 256-bit vectors **
AVX-512 AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and implemented in Intel's Xeon Phi x200 (Knights Landing) and Skylake-X CPUs; t ...
(including FP16) is present but disabled by default to match E-cores. On early revisions of microprocessors it still can be enabled on some motherboards with some BIOS versions by disabling the E-cores. Intel has physically fused off AVX-512 on later revisions of Alder Lake CPUs manufactured in early 2022 and onward. ** ~18% IPC uplift. * Gracemont efficient cores ("E-cores") ** Aggregated into 4-core modules with a shared
L2 cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, whic ...
** 256 reorder-buffer entries (up from 208 in Tremont) ** 17 execution ports (up from 12) **
AVX2 Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bri ...
, FMA and AVX-VNNI ** Skylake-like IPC. * New instruction set extensions: ** PTWRITE ** SERIALIZE ** HRESET * Up to 1 TB/s interconnect between cores * Intel Thread Director (only for CPUs with P and E cores), which is a marketing name for Enhanced Hardware Feedback Interface (EHFI). This is a hardware technology to assist the OS thread scheduler with more efficient load distribution between heterogeneous CPU cores. Enabling this new capability requires support in the operating system. * Architectural last branch records (LBRs) * Hypervisor-managed linear address translation (HLAT) * Control-flow enforcement technology ( CET), including support for indirect branch tracking (IBT) and
shadow stack A shadow is a dark area where light from a light source is blocked by an opaque object. It occupies all of the three-dimensional volume behind an object with light in front of it. The cross section of a shadow is a two-dimensional silhouette, ...
(SS) * 4–30 MB
L3 cache A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, wh ...
* Cores: ** up to 8 P-cores and 8 E-cores on desktop ** up to 6 P-cores and 8 E-cores on mobile (UP3 designs) ** up to 2 P-cores and 8 E-cores on ultra mobile (UP4 designs) ** only P-cores feature
hyper-threading Hyper-threading (officially called Hyper-Threading Technology or HT Technology and abbreviated as HTT or HT) is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve parallelization of computations (doing multipl ...


GPU

* Intel Xe (Gen 12.2) GPU * Up to 96 EU on mobile and 32 EU on desktop


I/O

*
LGA 1700 LGA 1700 (Socket V) is a zero insertion force flip-chip land grid array (LGA) socket, compatible with Intel desktop processors Alder Lake and Raptor Lake, which was first released in November 2021. LGA 1700 is designed as a replacement for L ...
socket for desktop processors. * BGA Type3 and Type4 HDI for mobile processors * 20
PCIe PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
lanes from CPU ** 16 PCIe 5.0 lanes ** 4 PCIe 4.0 lanes * Chipset link - DMI 4.0 ×8 link with Intel 600 series PCH chipsets *
DDR5 Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM, DDR5 was planned to reduce power consumption, while doubling bandwidth. Th ...
,
DDR4 Double Data Rate 4 Synchronous Dynamic Random-Access Memory (DDR4 SDRAM) is a type of synchronous dynamic random-access memory with a high bandwidth (" double data rate") interface. Released to the market in 2014, it is a variant of dynamic ran ...
,
LPDDR5 Low-Power Double Data Rate (LPDDR), also known as LPDDR SDRAM, is a type of synchronous dynamic random-access memory that consumes less power and is targeted for mobile computers and devices such as mobile phones. Older variants are also known a ...
, and
LPDDR4 Low-Power Double Data Rate (LPDDR), also known as LPDDR SDRAM, is a type of synchronous dynamic random-access memory that consumes less power and is targeted for mobile computers and devices such as mobile phones. Older variants are also known ...
memory support ** Up to DDR4-3200 ** Up to DDR5-4800 ** XMP 3.0 ** Dynamic Memory Boost * Integrated Thunderbolt 4 and
WiFi 6E IEEE 802.11ax, officially marketed by the Wi-Fi Alliance as (2.4 GHz and 5 GHz) and (6 GHz), is an IEEE standard for wireless local-area networks (WLANs) and the successor of 802.11ac. It is also known as ''High Efficiency'' , for ...
support


Dies

For the Alder Lake generation, Intel will initially produce 4 different dies. Each die has a different number of P-cores (P) and E-cores (E) and GPU Execution Units.


Software support

Alder Lake requires special support from the operating system due to its relatively unusual-for-x86 hybrid nature. For software unable to be upgraded, a
UEFI UEFI (Unified Extensible Firmware Interface) is a set of specifications written by the UEFI Forum. They define the architecture of the platform firmware used for booting and its interface for interaction with the operating system. Examples ...
-provided compatibility mode may be used to disable the E cores; it is enabled by the user turning on scroll lock.


CPUID incoherence

The P and E cores of early versions of Alder Lake CPUs reported different
CPUID In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from CPU IDentification) allowing software to discover details of the processor. It was introduced by Intel ...
models. This has caused issues with
digital rights management Digital rights management (DRM) is the management of legal access to digital content. Various tools or technological protection measures (TPM) such as access control technologies can restrict the use of proprietary hardware and copyrighted work ...
systems that perceive the P and E cores as being separate computers, and falsely enforce
license A license (or licence) is an official permission or permit to do, use, or own something (as well as the document of that permission or permit). A license is granted by a party (licensor) to another party (licensee) as an element of an agreeme ...
restrictions preventing a particular piece of software from being executed on more than one device at a time. Intel published a list of PC games it identified as having this compatibility issue, and stated that it was working with publishers to develop patches. Some of the games were identified by Intel as only having this bug on
Windows 10 Windows 10 is a major release of Microsoft's Windows NT operating system. It is the direct successor to Windows 8.1, which was released nearly two years earlier. It was released to manufacturing on July 15, 2015, and later to retail on ...
, and functioning correctly on
Windows 11 Windows 11 is the latest major release of Microsoft's Windows NT operating system, released in October 2021. It is a free upgrade to its predecessor, Windows 10 (2015), and is available for any Windows 10 devices that meet the new Windows 11 ...
(with some of them dependent on Windows 11 patches scheduled to be released in November 2021). ExamSoft similarly stated that its monitoring software for educational assessments (such as the
bar examination A bar examination is an examination administered by the bar association of a jurisdiction that a lawyer must pass in order to be admitted to the bar of that jurisdiction. Australia Administering bar exams is the responsibility of the bar associ ...
) was similarly incompatible with Alder Lake CPUs due to checks detecting
virtual machines In computing, a virtual machine (VM) is the virtualization/ emulation of a computer system. Virtual machines are based on computer architectures and provide functionality of a physical computer. Their implementations may involve specialized hard ...
. This problem has been fixed in a
microcode In processor design, microcode (μcode) is a technique that interposes a layer of computer organization between the central processing unit (CPU) hardware and the programmer-visible instruction set architecture of a computer. Microcode is a la ...
update. The P and E cores now return the same CPUID when both are enabled. A different CPUID is reported when E cores are disabled and only P cores are enabled. The
AVX-512 AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and implemented in Intel's Xeon Phi x200 (Knights Landing) and Skylake-X CPUs; t ...
instruction set In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an ...
extension is implemented in the P cores but disabled due to incompatibility with the E cores.
Hacker A hacker is a person skilled in information technology who uses their technical knowledge to achieve a goal or overcome an obstacle, within a computerized system by non-standard means. Though the term ''hacker'' has become associated in popu ...
s have shown that it is possible to enable the AVX-512 instructions on the P cores when the E cores are disabled and an old microcode version is used. There are minor differences between the behavior of the two cores with regard to an undefined overflow flag in certain bitwise operations.


Scheduler support

Alder Lake's CPU topology has performance implications, especially for gaming environments where the developers are not used to
NUMA Nuclear mitotic apparatus protein 1 is a protein that in humans is encoded by the ''NUMA1'' gene. Interactions Nuclear mitotic apparatus protein 1 has been shown to interact with PIM1, Band 4.1, GPSM2 G-protein-signaling modulator 2, also ca ...
setups. Microsoft added support for Intel Thread Director (ITD) in
Windows 11 Windows 11 is the latest major release of Microsoft's Windows NT operating system, released in October 2021. It is a free upgrade to its predecessor, Windows 10 (2015), and is available for any Windows 10 devices that meet the new Windows 11 ...
. A wide variety of inputs, including whether a process' window is in the foreground, feeds into the ITD. The ITD can function to a lesser extent with the OS providing less or no cooperation. Support in Linux is merged in kernel 5.18 but this alone is not sufficient until the kernel gets hints from userspace in order to schedule tasks to run on certain types of cores.


Blu-Ray DRM support

The CPU family no longer features Intel SGX which is a requirement for playing UltraHD
Blu-Ray The Blu-ray Disc (BD), often known simply as Blu-ray, is a digital optical disc data storage format. It was invented and developed in 2005 and released on June 20, 2006 worldwide. It is designed to supersede the DVD format, and capable of st ...
disks.


List of 12th generation Alder Lake processors


Desktop processors (Alder Lake-S)

* All the CPUs support up to 128 GB of DDR4-3200 or DDR5-4800 RAM in dual channel mode. * All the CPUs support 16x
PCI Express PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common ...
Gen 5 and 4x PCI Express Gen 4 lanes, but support may vary depending on motherboard and chipsets. * Models without the F suffix feature either of the following integrated UHD Graphics GPUs, all with base frequency of 300 MHz: ** UHD Graphics 770 with 32 EUs, ** UHD Graphics 730 with 24 EUs, or ** UHD Graphics 710 with 16 EUs. * By default, Alder Lake CPUs are configured to run at Turbo Power at all times and Base Power is only guaranteed when P-Cores/E-cores do ''not'' exceed the base clock rate. * Max Turbo Power: the maximum sustained (> 1 s) power dissipation of the processor as limited by current and/or temperature controls. Instantaneous power may exceed Maximum Turbo Power for short durations (≤ 10 ms). Maximum Turbo Power is configurable by system vendor and can be system specific. * CPUs in bold below feature
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct n-bit data corruption which occurs in memory. ECC memory is used in most computers where data corruption c ...
support only when paired with a motherboard based on the W680 chipset. * By default, Core i9-12900KS achieves 5.5 GHz only when using Thermal Velocity Boost.


Mobile processors


Alder Lake-HX

* CPUs in bold below feature
ECC memory Error correction code memory (ECC memory) is a type of computer data storage that uses an error correction code (ECC) to detect and correct n-bit data corruption which occurs in memory. ECC memory is used in most computers where data corruption c ...
support only when paired with a motherboard based on the WM690 chipset.


Alder Lake-H


Alder Lake-P


Alder Lake-U


Processors for Internet of Things (IoT) devices and embedded systems (Alder Lake-PS)

Most of these processors are identical to the corresponding Alder Lake-H and Alder Lake-U processors (without the L suffix) listed above.


High-power


Low-power


See also

*
Intel Core Intel Core is a line of streamlined midrange consumer, workstation and enthusiast computer central processing units (CPUs) marketed by Intel Corporation. These processors displaced the existing mid- to high-end Pentium processors at the time o ...
* Intel Lakefield *
Sapphire Rapids Sapphire Rapids is a codename for Intel's server (fourth generation Xeon Scalable) and workstation processors based on Intel 7. Sapphire Rapids was intended as part of the Eagle Stream server platform. In addition, it will be powering Aurora, a ...
, a codename for Intel's next generation Xeon server processors based on Intel 7 * List of Intel CPU microarchitectures


References

{{Intel processor roadmap Intel x86 microprocessors