Altos Design Automation, Inc. was an
electronic design automation
Electronic design automation (EDA), also referred to as electronic computer-aided design (ECAD), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards. The tools work together ...
software company. Altos developed and marketed cell and
semiconductor
intellectual property (IP) characterization tools that created library views
for timing,
signal integrity
Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage (or current) waveform. However, digital signals are fundamentally analog in nature, ...
and power analysis and optimization. The Altos
tools were fully automated and the company claimed that its tools are
extremely fast. The Altos tools were used by engineers employing both
corner-based and statistical-based design implementation flows to reduce
time-to -market and improve yield.
Altos was founded in January 2005 in Santa Clara,
California by former employees of Cadence Design Systems. All members of the
team worked at CadMOS where they were responsible for the development of
Signal Integrity analysis tools for both cell- and transistor-level digital
IC designers. In May 2011 Altos was acquired by Cadence.
Cadence Acquires Altos Design Automation
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Products
Variety creates statistical timing cell models that represent the non-linear impact of any number of systematic and random parameter variations. All library timing data is characterized for variation including delays, transitions, timing constraints, and pin capacitances. Variety generates statistical static timing analysis Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, in recent years the increased variation in semiconductor devices and interconnect has introduced a numb ...
(SSTA) models for a number of commercial SSTA products from a single characterization run.
Liberate is an automated library characterization tool for standard cells and I/Os that serves existing static timing analyzers. Liberate takes in a Spice netlist and Spice subcircuits, and automatically generates a characterized cell library. It supports both Composite Current Source (CCS) model backed by Synopsys and the Effective Current Source Model (ECSM) backed by Cadence Design Systems.
Footnotes
References
"Fireside Chat: Rick Lucier and Jim McCanny"
''EDACafe'', 2008-01-28.
"The 'Inconvenient Truth' of statistical design"
''SCDsource'', 2007-12-05.
"Where's the value in DFM? D or M?"
''Chip Design'', 2007-03-01.
"Altos closes $1.5M, signs Jim Hogan"
''EE Times'', 2007-01-05.
"Firms partner on standard statistical analysis library format"
''EE Times'', 2006-07-25.
"What's Hot at DAC?"
''EE Times'', 2006-07-17.
"Startup to 'Liberate' library characterization"
''EE Times'', 2006-07-03.
External links
* http://www.altos-da.com
Electronic design automation companies
Companies based in San Jose, California