The ARM Advanced Microcontroller Bus Architecture (AMBA) is an open-standard, on-chip interconnect specification for the connection and management of functional blocks in

system-on-a-chip A system on a chip or system-on-chip (SoC ; pl. ''SoCs'' ) is an integrated circuit that integrates most or all components of a computer or other electronic system. These components almost always include a central processing unit (CPU), memor ...

(SoC) designs. It facilitates development of multi-processor designs with large numbers of controllers and components with a bus architecture. Since its inception, the scope of AMBA has, despite its name, gone far beyond microcontroller devices. Today, AMBA is widely used on a range of

ASIC An application-specific integrated circuit (ASIC ) is an integrated circuit (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a digital voice recorder or a high-effici ...

and SoC parts including applications processors used in modern portable mobile devices like

smartphones A smartphone is a Mobile device, portable computer device that combines Mobile phone, mobile telephone and Mobile computing, computing functions into one unit. They are distinguished from feature phones by their stronger hardware capabilities ...

. AMBA is a registered trademark of

ARM Ltd Arm is a British semiconductor and software design company based in Cambridge, England. Its primary business is in the design of ARM processors (CPUs). It also designs other chips, provides software development tools under the DS-5, RealView a ...

. AMBA was introduced by ARM in 1996. The first AMBA buses were the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). In its second version, AMBA 2 in 1999, ARM added AMBA High-performance Bus (AHB) that is a single clock-edge protocol. In 2003, ARM introduced the third generation, AMBA 3, including Advanced eXtensible Interface (AXI) to reach even higher performance interconnect and the Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug and trace solution. In 2010 the AMBA 4 specifications were introduced starting with AMBA 4 AXI4, then in 2011 extending system-wide coherency with AMBA 4 AXI Coherency Extensions (ACE). In 2013 the AMBA 5 Coherent Hub Interface (CHI) specification was introduced, with a re-designed high-speed transport layer and features designed to reduce congestion. These protocols are today the

de facto standard A ''de facto'' standard is a custom or convention that has achieved a dominant position by public acceptance or market forces (for example, by early entrance to the market). is a Latin phrase (literally "in fact"), here meaning "in practice but ...

for embedded processor bus architectures because they are well documented and can be used without royalties.

Design principles

An important aspect of an SoC is not only which components or blocks it houses, but also how they interconnect. AMBA is a solution for the blocks to interface with each other. The objective of the AMBA specification is to: *facilitate ''right-first-time'' development of embedded microcontroller products with one or more CPUs, GPUs or signal processors, *be technology independent, to allow reuse of

IP core In electronic design, a semiconductor intellectual property core (SIP core), IP core, or IP block is a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of one party. IP cores can be licensed to ...

s, peripheral and system macrocells across diverse IC processes, *encourage modular system design to improve processor independence, and the development of reusable peripheral and system IP libraries *minimize silicon infrastructure while supporting high performance and low power on-chip communication.

AMBA protocol specifications

The AMBA specification defines an on-chip communications standard for designing high-performance embedded microcontrollers. It is supported by ARM Limited with wide cross-industry participation. The ''AMBA 5 specification'' defines the following buses/interfaces: * AXI5, AXI5-Lite and ACE5 Protocol Specification * Advanced High-performance Bus (AHB5, AHB-Lite) * Coherent Hub Interface (CHI) * Distributed Translation Interface (DTI) * Generic Flash Bus (GFB) The ''AMBA 4 specification'' defines following buses/interfaces: *AXI Coherency Extensions (ACE) - widely used on the latest ARM Cortex-A processors including Cortex-A7 and Cortex-A15 *AXI Coherency Extensions Lite (ACE-Lite) *Advanced Extensible Interface 4 (AXI4) *Advanced Extensible Interface 4 Lite (AXI4-Lite) *Advanced Extensible Interface 4 Stream (AXI4-Stream v1.0) *Advanced Trace Bus (ATB v1.1) *Advanced Peripheral Bus (APB4 v2.0) *AMBA Low Power Interfaces (Q-Channel and P-Channel) AMBA 3 specification defines four buses/interfaces: * Advanced eXtensible Interface (AXI3 or AXI v1.0) - widely used on ARM Cortex-A processors including Cortex-A9 *Advanced High-performance Bus Lite (AHB-Lite v1.0) *Advanced Peripheral Bus (APB3 v1.0) *Advanced Trace Bus (ATB v1.0) AMBA 2 specification defines three buses/interfaces: *Advanced High-performance Bus (AHB) - widely used on ARM7, ARM9 and ARM Cortex-M based designs *Advanced System Bus (ASB) *Advanced Peripheral Bus (APB2 or APB) AMBA specification (First version) defines two buses/interfaces: *Advanced System Bus (ASB) *Advanced Peripheral Bus (APB) The timing aspects and the

voltage Voltage, also known as electric pressure, electric tension, or (electric) potential difference, is the difference in electric potential between two points. In a static electric field, it corresponds to the work needed per unit of charge t ...

levels on the bus are not dictated by the specifications.

AXI Coherency Extensions (ACE and ACE-Lite)

ACE, defined as part of the AMBA 4 specification, extends AXI with additional signalling introducing system wide coherency. This system coherency allows multiple processors to share memory and enables technology like ARM's

big.LITTLE ARM big.LITTLE is a heterogeneous computing architecture developed by ARM Holdings, coupling relatively battery-saving and slower processor cores (''LITTLE'') with relatively more powerful and power-hungry ones (''big''). Typically, only one " ...

processing. The ACE-Lite protocol enables one-way coherency, also known as I/O coherency; for example, a network interface that can read from the caches of a fully coherent ACE processor.

Advanced eXtensible Interface (AXI)

AXI, the third generation of AMBA interface defined in the AMBA 3 specification, is targeted at high performance, high clock frequency system designs and includes features that make it suitable for high speed sub-micrometer interconnect: * separate address/control and data phases * support for unaligned data transfers using byte strobes * burst based transactions with only start address issued * issuing of multiple outstanding addresses with out of order responses * easy addition of register stages to provide timing closure.

Advanced High-performance Bus (AHB)

AHB is a bus protocol introduced in Advanced Microcontroller Bus Architecture version 2 published by

company. In addition to previous release, it has the following features: * large bus-widths (64/128/256/512/1024 bit). A simple transaction on the AHB consists of an address phase and a subsequent data phase (without wait states: only two bus-cycles). Access to the target device is controlled through a MUX (non-tristate), thereby admitting bus-access to one bus-master at a time. AHB-Lite is a subset of AHB formally defined in the AMBA 3 standard. This subset simplifies the design for a bus with a single master.

Advanced Peripheral Bus (APB)

APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals. This bus has an address and data phase similar to AHB, but a much reduced, low complexity signal list (for example no bursts). Furthermore, it is an interface designed for a low frequency system with a low bit width (32 bits).

AMBA products

A family of synthesizable intellectual property ( IP) cores ''AMBA Products'' is licensable from ARM Limited that implement a digital bus in an SoC for the efficient moving and storing of data using the AMBA protocol specifications. The AMBA family includes AMBA Network Interconnect (CoreLink NIC-400), Cache Coherent Interconnect (CoreLink CCI-500),

SDRAM Synchronous dynamic random-access memory (synchronous dynamic RAM or SDRAM) is any DRAM where the operation of its external pin interface is coordinated by an externally supplied clock signal. DRAM integrated circuits (ICs) produced from the ...

memory controllers (CoreLink DMC-400),

DMA DMA may refer to: Arts * ''DMA'' (magazine), a defunct dance music magazine * Dallas Museum of Art, an art museum in Texas, US * Danish Music Awards, an award show held in Denmark * BT Digital Music Awards, an annual event in the UK * Doctor of M ...

controllers (CoreLink DMA-230, DMA-330), level 2 cache controllers (L2C-310), etc. A number of manufacturers utilize AMBA buses for non-ARM designs. As an example

Infineon Infineon Technologies AG is a German semiconductor manufacturer founded in 1999, when the semiconductor operations of the former parent company Siemens AG were spun off. Infineon has about 50,280 employees and is one of the ten largest semicond ...

uses an AMBA bus for the ADM5120 SoC based on the

MIPS architecture MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA)Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, ...

Competitors

* Wishbone from OpenCores – Free and open bus architecture (formerly from Silicore) *

CoreConnect __NOTOC__ CoreConnect is a microprocessor bus-architecture from IBM for system-on-a-chip (SoC) designs. It was designed to ease the integration and reuse of processor, system, and peripheral cores within standard and custom SoC designs. As a stan ...

bus technology from IBM, used in IBM's embedded

PowerPC PowerPC (with the backronym Performance Optimization With Enhanced RISC – Performance Computing, sometimes abbreviated as PPC) is a reduced instruction set computer (RISC) instruction set architecture (ISA) created by the 1991 Apple– IBM ...

, but also in many other SoC-like systems with the

Xilinx Xilinx, Inc. ( ) was an American technology and semiconductor company that primarily supplied programmable logic devices. The company was known for inventing the first commercially viable field-programmable gate array (FPGA) and creating the fi ...

MicroBlaze or similar cores * IPBus by IDT *

Avalon Avalon (; la, Insula Avallonis; cy, Ynys Afallon, Ynys Afallach; kw, Enys Avalow; literally meaning "the isle of fruit r appletrees"; also written ''Avallon'' or ''Avilion'' among various other spellings) is a mythical island featured in th ...

– proprietary bus system by

Altera Altera Corporation was a manufacturer of programmable logic devices (PLDs) headquartered in San Jose, California. It was founded in 1983 and acquired by Intel in 2015. The main product lines from Altera were the flagship Stratix series, mid-ra ...

for use in their

Nios II Nios II is a 32-bit embedded processor architecture designed specifically for the Altera family of field-programmable gate array (FPGA) integrated circuits. Nios II incorporates many enhancements over the original Nios architecture, making it mo ...

SoCs * Open Core Protocol (OCP) from

Accellera Accellera Systems Initiative (Accellera) is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation (EDA) and integrated circuit (IC) design and manufact ...

HyperTransport HyperTransport (HT), formerly known as Lightning Data Transport, is a technology for interconnection of computer processors. It is a bidirectional serial/ parallel high- bandwidth, low- latency point-to-point link that was introduced on Apri ...

(HT) from AMD (though this is an off-chip interface, not on-chip bus) * QuickPath Interconnect (QPI) by

Intel Intel Corporation is an American multinational corporation and technology company headquartered in Santa Clara, California, Santa Clara, California. It is the world's largest semiconductor chip manufacturer by revenue, and is one of the devel ...

(though this is an off-chip interface, not on-chip bus) * virtual share from PICC - free and open source * TileLink - Free and open bus architecture from CHIPS Alliance