Argonaut RISC Core (ARC) is a family of 32-bit and 64-bit reduced instruction set computer (RISC)

central processing unit A central processing unit (CPU), also called a central processor, main processor, or just processor, is the primary Processor (computing), processor in a given computer. Its electronic circuitry executes Instruction (computing), instructions ...

s (CPUs) originally designed by ARC International. ARC processors are configurable and extensible for a wide range of uses in

system on a chip A system on a chip (SoC) is an integrated circuit that combines most or all key components of a computer or Electronics, electronic system onto a single microchip. Typically, an SoC includes a central processing unit (CPU) with computer memory, ...

(SoC) devices, including storage, digital home, mobile, automotive, and

Internet of things Internet of things (IoT) describes devices with sensors, processing ability, software and other technologies that connect and exchange data with other devices and systems over the Internet or other communication networks. The IoT encompasse ...

(IoT) applications. They have been licensed by more than 200 organizations and are shipped in more than 1.5 billion products per year. ARC processors employ the 16-/32-bit ARCompact compressed instruction set

instruction set architecture In computer science, an instruction set architecture (ISA) is an abstract model that generally defines how software controls the CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, ...

(ISA) that provides good performance and code density for embedded and host SoC applications.

History

The ARC concept was developed initially within Argonaut Games through a series of 3D pipeline development projects starting with the Super FX chip for the

Super Nintendo Entertainment System The Super Nintendo Entertainment System, commonly shortened to Super Nintendo, Super NES or SNES, is a Fourth generation of video game consoles, 16-bit home video game console developed by Nintendo that was released in 1990 in Japan, 1991 in No ...

. In 1995, Argonaut was split into Argonaut Technologies Limited (ATL), which had a variety of technology projects, and Argonaut Software Limited (ASL). At the start of 1996, the General Manager of Argonaut, John Edelson, started reducing ATL projects such as BRender and

motion capture Motion capture (sometimes referred as mocap or mo-cap, for short) is the process of recording high-resolution motion (physics), movement of objects or people into a computer system. It is used in Military science, military, entertainment, sports ...

and investing in the development of the ARC concept. In September 1996 Rick Clucas decided that the value of the ARC processor was in other people using it rather than Argonaut doing projects using it and asked Bob Terwilliger to join as CEO; Rick Clucas then took on the role of CTO. In 1997, following investment by Apax Partners, ATL became ARC International and fully independent from Argonaut Games. Before their

initial public offering An initial public offering (IPO) or stock launch is a public offering in which shares of a company are sold to institutional investors and usually also to retail (individual) investors. An IPO is typically underwritten by one or more investm ...

on the London Stock Exchange, underwritten by Goldman Sachs and five other investment banks, three related technology companies were acquired: MetaWare in

Santa Cruz, California Santa Cruz (Spanish language, Spanish for "Holy Cross") is the largest city and the county seat of Santa Cruz County, California, Santa Cruz County, in Northern California. As of the 2020 United States census, 2020 census, the city population ...

(development and modeling software), VAutomation in Nashua, New Hampshire (peripheral semiconductor IP), and Precise Software in Nepean, Ontario (RTOS). In 2009, ARC International was acquired by Virage Logic. In 2010, Virage was acquired by Synopsys, and ARC processors became part of the Synopsys DesignWare series. In April 2020 Synopsys released the ARCv3 ISA with 64-bit support. In November 2023, Synopsys released the

RISC-V RISC-V (pronounced "risk-five") is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project commenced in 2010 at the University of California, Berkeley. It transfer ...

compatible ''ARC-V'' processor IP as an extension of its ARC product line.

Design configuration

Designers can differentiate their products by using patented configuration technology to tailor each ARC processor instance to meet specific performance, power and area requirements. Configuration of the ARC processors occurs at design time, using the ARChitect processor configurator. The core was designed to be extensible, allowing designers to add their own custom instructions that can significantly increase performance or reduce power consumption. Unlike most embedded microprocessors, extra instructions, registers, and functions can be added in a modular fashion. Customers analyse the task, break down the operations, and then choose the appropriate extensions, or develop their own, to create their own custom microprocessor. They might optimise for speed, energy efficiency, or code density. Extensions can include, for example, a memory management unit (MMU), a fast multiplier–accumulator, a Universal Serial Bus ( USB) host, a Viterbi path decoder, or a user's proprietary RTL functions. The processors are synthesizable and can be implemented in any foundry or process, and are supported by a complete suite of development tools.

References

External links

* {{DEFAULTSORT:Arc International Embedded microprocessors System on a chip

History

Design configuration

See also

References

Further reading

External links