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Permuted Congruential Generator
A permuted congruential generator (PCG) is a pseudorandom number generation algorithm developed in 2014 which applies an output permutation function to improve the statistical properties of a modulo-2n linear congruential generator. It achieves excellent statistical performance with small and fast code, and small state size. A PCG differs from a classical linear congruential generator (LCG) in three ways: * the LCG modulus and state is larger, usually twice the size of the desired output, * it uses a power-of-2 modulus, which results in a particularly efficient implementation with a full period generator and unbiased output bits, and * the state is not output directly, but rather the most significant bits of the state are used to select a bitwise rotation or shift which is applied to the state to produce the output. It is the variable rotation which eliminates the problem of a short period in the low-order bits that power-of-2 LCGs suffer from. Variants The PCG family includes ...
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Pseudorandom Number Generation
A pseudorandom number generator (PRNG), also known as a deterministic random bit generator (DRBG), is an algorithm for generating a sequence of numbers whose properties approximate the properties of sequences of random numbers. The PRNG-generated sequence is not truly random, because it is completely determined by an initial value, called the PRNG's ''seed'' (which may include truly random values). Although sequences that are closer to truly random can be generated using hardware random number generators, ''pseudorandom number generators'' are important in practice for their speed in number generation and their reproducibility. PRNGs are central in applications such as simulations (e.g. for the Monte Carlo method), electronic games (e.g. for procedural generation), and cryptography. Cryptographic applications require the output not to be predictable from earlier outputs, and more elaborate algorithms, which do not inherit the linearity of simpler PRNGs, are needed. Good stati ...
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Instruction-level Parallelism
Instruction-level parallelism (ILP) is the parallel or simultaneous execution of a sequence of instructions in a computer program. More specifically ILP refers to the average number of instructions run per step of this parallel execution. Discussion ILP must not be confused with concurrency. In ILP there is a single specific thread of execution of a process. On the other hand, concurrency involves the assignment of multiple threads to a CPU's core in a strict alternation, or in true parallelism if there are enough CPU cores, ideally one core for each runnable thread. There are two approaches to instruction-level parallelism: hardware and software. Hardware level works upon dynamic parallelism, whereas the software level works on static parallelism. Dynamic parallelism means the processor decides at run time which instructions to execute in parallel, whereas static parallelism means the compiler decides which instructions to execute in parallel. The Pentium processor ...
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Pseudorandom Number Generators
A pseudorandom number generator (PRNG), also known as a deterministic random bit generator (DRBG), is an algorithm for generating a sequence of numbers whose properties approximate the properties of sequences of random numbers. The PRNG-generated sequence is not truly random, because it is completely determined by an initial value, called the PRNG's ''seed'' (which may include truly random values). Although sequences that are closer to truly random can be generated using hardware random number generators, ''pseudorandom number generators'' are important in practice for their speed in number generation and their reproducibility. PRNGs are central in applications such as simulations (e.g. for the Monte Carlo method), electronic games (e.g. for procedural generation), and cryptography. Cryptographic applications require the output not to be predictable from earlier outputs, and more elaborate algorithms, which do not inherit the linearity of simpler PRNGs, are needed. Good statist ...
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Xoroshiro128+
xoroshiro128+ (named after its operations: XOR, rotate, shift, rotate) is a pseudorandom number generator intended as a successor to xorshift+. Instead of perpetuating Marsaglia's tradition of xorshift as a basic operation, xoroshiro128+ uses a shift/rotate-based linear transformation designed by Sebastiano Vigna in collaboration with David Blackman. The result is a significant improvement in speed and statistical quality. Statistical Quality The lowest bits of the output generated by xoroshiro128+ have low quality. The authors of xoroshiro128+ acknowledge that it does not pass all statistical tests, stating This is xoroshiro128+ 1.0, our best and fastest small-state generator for floating-point numbers. We suggest to use its upper bits for floating-point generation, as it is slightly faster than xoroshiro128**. It passes all tests we are aware of except for the four lower bits, which might fail linearity tests (and just those), so if low linear complexity ...
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ACM Transactions On Mathematical Software
''ACM Transactions on Mathematical Software'' (''TOMS'') is a quarterly scientific journal that aims to disseminate the latest findings of note in the field of numeric, symbolic, algebraic, and geometric computing applications. It is one of the oldest scientific journals specifically dedicated to mathematical algorithms and their implementation in software, and has been published since March 1975 by the Association for Computing Machinery (ACM). The journal is described as follows on thTOMS Homepage of the ACM Digital Librarypage: The purpose of the journal was laid out by its founding editor, John Rice, in the inaugural issue. The decision to found the journal came out of the 1970 Mathematical Software Symposium at Purdue University, also organized by Rice, who then negotiated with both SIAM and the ACM regarding its publication. The journal publishes two kinds of articles: Regular research papers that advance the development of algorithms and software for mathematical computi ...
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Mersenne Twister
The Mersenne Twister is a general-purpose pseudorandom number generator (PRNG) developed in 1997 by and . Its name derives from the fact that its period length is chosen to be a Mersenne prime. The Mersenne Twister was designed specifically to rectify most of the flaws found in older PRNGs. The most commonly used version of the Mersenne Twister algorithm is based on the Mersenne prime 2^-1. The standard implementation of that, MT19937, uses a 32-bit word length. There is another implementation (with five variants) that uses a 64-bit word length, MT19937-64; it generates a different sequence. Application Software The Mersenne Twister is used as default PRNG by the following software: * Programming languages: Dyalog APL, IDL, R, Ruby, Free Pascal, PHP, Python (also available in NumPy, however the default was changed to PCG64 instead as of version 1.17),, CMU Common Lisp, Embeddable Common Lisp, Steel Bank Common Lisp, Julia (up to Julia 1.6 LTS, still available in ...
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Xorshift
Xorshift random number generators, also called shift-register generators, are a class of pseudorandom number generators that were invented by George Marsaglia. They are a subset of linear-feedback shift registers (LFSRs) which allow a particularly efficient implementation in software without the excessive use of sparse polynomials. They generate the next number in their sequence by repeatedly taking the exclusive or of a number with a bit-shifted version of itself. This makes execution extremely efficient on modern computer architectures, but it does not benefit efficiency in a hardware implementation. Like all LFSRs, the parameters have to be chosen very carefully in order to achieve a long period. For execution in software, xorshift generators are among the fastest non- cryptographically-secure random number generators, requiring very small code and state. However, they do not pass every statistical test without further refinement. This weakness is amended by combining them wi ...
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TestU01
TestU01 is a software library, implemented in the ANSI C language, that offers a collection of utilities for the empirical randomness testing of random number generators (RNGs).The TestU01 web site
The library was first introduced in 2007 by Pierre L’Ecuyer and Richard Simard of the .Pierre L’Ecuyer & Richard Simard (2007),
TestU01: A Software Library in ANSI C for Empirical Testing of Random Number Generators
, ''
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Lehmer Random Number Generator
The Lehmer random number generator (named after D. H. Lehmer), sometimes also referred to as the Park–Miller random number generator (after Stephen K. Park and Keith W. Miller), is a type of linear congruential generator (LCG) that operates in multiplicative group of integers modulo n. The general formula is : X_ = a \cdot X_k \bmod m, where the modulus ''m'' is a prime number or a power of a prime number, the multiplier ''a'' is an element of high multiplicative order modulo ''m'' (e.g., a primitive root modulo ''n''), and the seed ''X'' is coprime to ''m''. Other names are multiplicative linear congruential generator (MLCG) and multiplicative congruential generator (MCG). Parameters in common use In 1988, Park and Miller suggested a Lehmer RNG with particular parameters ''m'' = 2 − 1 = 2,147,483,647 (a Mersenne prime ''M'') and ''a'' = 7 = 16,807 (a primitive root modulo ''M''), now known as MINSTD. Although MINSTD was later criticized by Marsaglia and Sulliva ...
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Superscalar Processor
A superscalar processor is a CPU that implements a form of parallelism called instruction-level parallelism within a single processor. In contrast to a scalar processor, which can execute at most one single instruction per clock cycle, a superscalar processor can execute more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different execution units on the processor. It therefore allows more throughput (the number of instructions that can be executed in a unit of time) than would otherwise be possible at a given clock rate. Each execution unit is not a separate processor (or a core if the processor is a multi-core processor), but an execution resource within a single CPU such as an arithmetic logic unit. In Flynn's taxonomy, a single-core superscalar processor is classified as an SISD processor (single instruction stream, single data stream), though a single-core superscalar processor that supports short vector operations coul ...
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Equidistribution
In mathematics, a sequence (''s''1, ''s''2, ''s''3, ...) of real numbers is said to be equidistributed, or uniformly distributed, if the proportion of terms falling in a subinterval is proportional to the length of that subinterval. Such sequences are studied in Diophantine approximation theory and have applications to Monte Carlo integration. Definition A sequence (''s''1, ''s''2, ''s''3, ...) of real numbers is said to be ''equidistributed'' on a non-degenerate interval 'a'', ''b''if for every subinterval 'c'', ''d''of 'a'', ''b''we have :\lim_= . (Here, the notation , ∩ 'c'', ''d'' denotes the number of elements, out of the first ''n'' elements of the sequence, that are between ''c'' and ''d''.) For example, if a sequence is equidistributed in , 2 since the interval .5, 0.9occupies 1/5 of the length of the interval , 2 as ''n'' becomes large, the proportion of the first ''n'' members of the sequence which fall between 0.5 and 0.9 must approach 1/5. L ...
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