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List Of VIA Eden Microprocessors
The Eden microprocessors from VIA Technologies are fifth- and sixth-generation CPUs targeted at the embedded market. Embedded processors Eden ESP "Samuel 2" (150 nm) * All models support: ''MMX, 3DNow!'' "Nehemiah" (130 nm) * All models support: ''MMX, SSE, VIA PadLock (AES, RNG)'' Eden-N "Nehemiah" (130 nm) * All models support: ''MMX, SSE, VIA PadLock (AES, RNG)'' * VIA PowerSaver supported Eden "Esther" (standard-voltage, 90 nm) * All models support: ''MMX, SSE, SSE2, SSE3, NX bit, VIA PadLock (SHA, AES, Montgomery Multiplier, RNG)'' * VIA PowerSaver supported with up to 8 ACPI P-states * Idle power 500 mW "Esther" (ultra-low-voltage, 90 nm) * All models support: ''MMX, SSE, SSE2, SSE3, NX bit, VIA PadLock (SHA, AES, Montgomery Multiplier, RNG)'' * VIA PowerSaver supported with up to 8 ACPI P-states Eden X2 "Eden X2" (40 nm) * All models support: ''MMX, SSE, SSE2, SSE3, x86-64, NX bit, x86 virtualization, VIA PadLock (SHA, AE ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
VIA Eden
VIA Eden is a name of a variant of VIA's C3/ C7 x86 processors, designed to be used in embedded devices. They have smaller package sizes, lower power consumption, and somewhat lower computing performance than their C equivalents, due to reduced clock rates. They are often used in EPIA mini-ITX, nano-ITX, and Pico-ITX motherboards. In addition to x86 instruction decoding, the processors have a second undocumented Alternate Instruction Set. The Eden is available in four main versions: * Eden ESP: Samuel 2 and Nehemiah cores (300 MHz-1.0 GHz) - EBGA 35mm×35mm package, 66/100/133 MHz FSB * Eden-N: Nehemiah core (533 MHz-1.0 GHz) - NanoBGA 15mm×15mm package, 133 MHz FSB * Eden: Esther core (400 MHz-1.2 GHz) - NanoBGA2 21mm×21mm package, 400 MT/s FSB * Eden ULV: Esther core (500 MHz-1.5 GHz) - NanoBGA2 21mm×21mm package, 400 MT/s FSB The Eden ULV 500 MHz was the first variant to achieve a TDP of 1W .http://www.viatech.com/en ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
NX Bit
The NX bit (no-execute) is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions or for storage of data, a feature normally only found in Harvard architecture processors. However, the NX bit is being increasingly used in conventional von Neumann architecture processors for security reasons. An operating system with support for the NX bit may mark certain areas of memory as non-executable. The processor will then refuse to execute any code residing in these areas of memory. The general technique, known as executable space protection, also called Write XOR Execute, is used to prevent certain types of malicious software from taking over computers by inserting their code into another program's data storage area and running their own code from within this section; one class of such attacks is known as the buffer overflow attack. The term NX bit originated with Advanced Micro Devices (AMD), as a marketing term. Intel markets the f ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
List Of VIA Microprocessors
This article lists x86-compliant microprocessors sold by VIA Technologies, grouped by technical merits: cores within same group have much in common. Cyrix design ( Cyrix III) * All models support: '' MMX, 3DNow!'' Centaur Technology design Cyrix III, C3 * All models support: '' MMX, 3DNow!'' C3, C7 * All models support: '' MMX, SSE'' * SSE2, SSE3, NX bit supported by Esther (C5J) Nano * See List of Nano microprocessors CHA * Currently in development. Details listed below are subject to change, * 8 cores + "NCORE" neural processor for AI acceleration. * supports: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AES AVX AVX2 FMA3 SHA AVX512 AVX512F AVX512CD AVX512BW AVX512DQ AVX512VL AVX512IFMA AVX512VBMI. See also * List of VIA C3 microprocessors * List of VIA C7 microprocessors * List of VIA Eden microprocessors * List of VIA Nano microprocessors References External links Via C3 product pageVia C7 product page Via Nano product page {{VI ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
AES-NI
An Advanced Encryption Standard instruction set is now integrated into many processors. The purpose of the instruction set is to improve the speed and security of applications performing encryption and decryption using Advanced Encryption Standard (AES). They are often implemented as instructions implementing a single round of AES along with a special version for the last round which has a slightly different method. The side channel attack surface of AES is reduced when implemented in an instruction set, compared to when AES is implemented in software only. x86 architecture processors AES-NI (or the Intel Advanced Encryption Standard New Instructions; AES-NI) was the first major implementation. AES-NI is an extension to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008. Instructions Intel The following Intel processors support the AES-NI instruction set: * Westmere based processors, specifically: ** Westme ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
VIA PadLock
VIA PadLock is a central processing unit (CPU) instruction set extension to the x86 microprocessor instruction set architecture (ISA) found on processors produced by VIA Technologies and Zhaoxin. Introduced in 2003 with the VIA Centaur CPUs, the additional instructions provide hardware-accelerated random number generation (RNG), Advanced Encryption Standard (AES), SHA-1, SHA256, and Montgomery modular multiplication. Instructions The PadLock instruction set can be divided into four subsets: * Random number generation (RNG) ** XSTORE: Store Available Random Bytes (aka XSTORERNG) ** REP XSTORE: Store ECX Random Bytes * Advanced cryptography engine (ACE) - for AES crypto; two versions ** REP XCRYPTECB: Electronic code book ** REP XCRYPTCBC: Cipher Block Chaining ** REP XCRYPTCTR: Counter Mode (ACE2) ** REP XCRYPTCFB: Cipher Feedback Mode ** REP XCRYPTOFB: Output Feedback Mode * SHA hash engine (PHE) ** REP XSHA1: Hash Function SHA-1 ** REP XSHA256: Hash Function SHA-256 * Mon ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
AVX2
Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge processor shipping in Q1 2011 and later by AMD with the Bulldozer processor shipping in Q3 2011. AVX provides new features, new instructions and a new coding scheme. AVX2 (also known as Haswell New Instructions) expands most integer commands to 256 bits and introduces new instructions. They were first supported by Intel with the Haswell processor, which shipped in 2013. AVX-512 expands AVX to 512-bit support using a new EVEX prefix encoding proposed by Intel in July 2013 and first supported by Intel with the Knights Landing co-processor, which shipped in 2016. In conventional processors, AVX-512 was introduced with Skylake server and HEDT processors in 2017. Advanced Vector Extensions AVX uses sixteen YMM registers to perform a s ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Advanced Vector Extensions
Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge processor shipping in Q1 2011 and later by AMD with the Bulldozer processor shipping in Q3 2011. AVX provides new features, new instructions and a new coding scheme. AVX2 (also known as Haswell New Instructions) expands most integer commands to 256 bits and introduces new instructions. They were first supported by Intel with the Haswell processor, which shipped in 2013. AVX-512 expands AVX to 512-bit support using a new EVEX prefix encoding proposed by Intel in July 2013 and first supported by Intel with the Knights Landing co-processor, which shipped in 2016. In conventional processors, AVX-512 was introduced with Skylake server and HEDT processors in 2017. Advanced Vector Extensions AVX uses sixteen YMM registers to perform a s ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SSE4
SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on September 27, 2006, at the Fall 2006 Intel Developer Forum, with vague details in a white paper; more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in Beijing, in the presentation. SSE4 is fully compatible with software written for previous generations of Intel 64 and IA-32 architecture microprocessors. All existing software continues to run correctly without modification on microprocessors that incorporate SSE4, as well as in the presence of existing and new applications that incorporate SSE4. SSE4 subsets Intel SSE4 consists of 54 instructions. A subset consisting of 47 instructions, referred to as ''SSE4.1'' in some Intel documentation, is available in Penryn. Additionally, ''SSE4.2'', a second subset consisting of the 7 remaining instructions, is first available in Nehalem-based Co ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
SSSE3
Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitecture on June 26, 2006 with the "Woodcrest" Xeons. SSSE3 has been referred to by the codenames Tejas New Instructions (TNI) or Merom New Instructions (MNI) for the first processor designs intended to support it. Functionality SSSE3 contains 16 new discrete instructions. Each instruction can act on 64-bit MMX or 128-bit XMM registers. Therefore, Intel's materials refer to 32 new instructions. They include: * Twelve instructions that perform horizontal addition or subtraction operations. * Six instructions that evaluate absolute values. * Two instructions that perform multiply-and-add operations and speed up the evaluation of dot products. * Two instructions that accelerate packed integer multiply operations and produce integer values wi ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
X86 Virtualization
x86 virtualization is the use of hardware-assisted virtualization capabilities on an x86/x86-64 CPU. In the late 1990s x86 virtualization was achieved by complex software techniques, necessary to compensate for the processor's lack of hardware-assisted virtualization capabilities while attaining reasonable performance. In 2005 and 2006, both Intel (VT-x) and AMD (AMD-V) introduced limited hardware virtualization support that allowed simpler virtualization software but offered very few speed benefits. Greater hardware support, which allowed substantial speed improvements, came with later processor models. Software-based virtualization The following discussion focuses only on virtualization of the x86 architecture protected mode. In protected mode the operating system kernel runs at a higher privilege such as ring 0, and applications at a lower privilege such as ring 3. In software-based virtualization, a host OS has direct access to hardware while the guest OSs have limited ac ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
X86-64
x86-64 (also known as x64, x86_64, AMD64, and Intel 64) is a 64-bit version of the x86 instruction set, first released in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mode. With 64-bit mode and the new paging mode, it supports vastly larger amounts of virtual memory and physical memory than was possible on its 32-bit predecessors, allowing programs to store larger amounts of data in memory. x86-64 also expands general-purpose registers to 64-bit, and expands the number of them from 8 (some of which had limited or fixed functionality, e.g. for stack management) to 16 (fully general), and provides numerous other enhancements. Floating-point arithmetic is supported via mandatory SSE2-like instructions, and x87/MMX style registers are generally not used (but still available even in 64-bit mode); instead, a set of 16 vector registers, 128 bits each, is used. (Each register can store one or two double-p ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Advanced Configuration And Power Interface
Advanced Configuration and Power Interface (ACPI) is an open standard that operating systems can use to discover and configure computer hardware components, to perform power management (e.g. putting unused hardware components to sleep), auto configuration (e.g. Plug and Play and hot swapping), and status monitoring. First released in December 1996, ACPI aims to replace Advanced Power Management (APM), the MultiProcessor Specification, and the Plug and Play BIOS (PnP) Specification. ACPI brings power management under the control of the operating system, as opposed to the previous BIOS-centric system that relied on platform-specific firmware to determine power management and configuration policies. The specification is central to the Operating System-directed configuration and Power Management (OSPM) system. ACPI defines hardware abstraction interfaces between the device's firmware (e.g. BIOS, UEFI), the computer hardware components, and the operating systems. Internally, ACPI a ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
