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IBM ZSeries
IBM Z is a family name used by IBM for all of its z/Architecture mainframe computers. In July 2017, with another generation of products, the official family was changed to IBM Z from IBM z Systems; the IBM Z family now includes the newest model, the IBM z16, as well as the z15, the z14, and the z13 (released under the IBM z Systems/IBM System z names), the IBM zEnterprise models (in common use the zEC12 and z196), the IBM System z10 models (in common use the z10 EC), the IBM System z9 models (in common use the z9EC) and ''IBM eServer zSeries'' models (in common use refers only to the z900 and z990 generations of mainframe). Architecture The ''zSeries,'' ''zEnterprise,'' ''System z'' and ''IBM Z'' families were named for their availability – ''z'' stands for zero downtime. The systems are built with spare components capable of hot failovers to ensure continuous operations. The IBM Z family maintains full backward compatibility. In effect, current systems are the direct, ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Common Criteria
The Common Criteria for Information Technology Security Evaluation (referred to as Common Criteria or CC) is an international standard ( ISO/IEC 15408) for computer security certification. It is currently in version 3.1 revision 5. Common Criteria is a framework in which computer system users can ''specify'' their security ''functional'' and ''assurance'' requirements (SFRs and SARs respectively) in a Security Target (ST), and may be taken from Protection Profiles (PPs). Vendors can then ''implement '' or make claims about the security attributes of their products, and testing laboratories can ''evaluate'' the products to determine if they actually meet the claims. In other words, Common Criteria provides assurance that the process of specification, implementation and evaluation of a computer security product has been conducted in a rigorous and standard and repeatable manner at a level that is commensurate with the target environment for use. Common Criteria maintains a list of ce ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
IBM Z13 (microprocessor)
The z13 is a microprocessor made by IBM for their z13 mainframe computers, announced on January 14, 2015. Manufactured at GlobalFoundries' East Fishkill, New York fabrication plant (formerly IBM's own plant). IBM stated that it is the world's fastest microprocessor and is about 10% faster than its predecessor the zEC12 in general single-threaded computing, but significantly more when doing specialized tasks. The IBM z13 is the last z Systems server to support running an operating system in ESA/390 architecture mode. However, all 24-bit and 31-bit problem-state application programs originally written to run on the ESA/390 architecture are unaffected by this change. Description The Processor Unit chip (PU chip) has an area of 678 mm2 and contains 3.99 billion transistors. It is fabricated using IBM's 22 nm CMOS silicon on insulator fabrication process, using 17 metal layers and supporting speeds of 5.0 GHz, which is less than its predecessor, the zEC12. The PU ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Computerworld
''Computerworld'' (abbreviated as CW) is an ongoing decades old professional publication which in 2014 "went digital." Its audience is information technology (IT) and business technology professionals, and is available via a publication website and as a digital magazine. As a printed weekly during the 1970s and into the 1980s, ''Computerworld'' was the leading trade publication in the data processing industry. Indeed, based on circulation and revenue it was one of the most successful trade publications in any industry. Later in the 1980s it began to lose its dominant position. It is published in many countries around the world under the same or similar names. Each country's version of ''Computerworld'' includes original content and is managed independently. The parent company of Computerworld US is IDG Communications. History The first issue was published in 1967. Going international The company IDG International Data Group (IDG, Inc.) is a market intelligence and demand ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Coupling Facility
In IBM System/390 and IBM Z mainframe computers, a Coupling Facility or CF is a piece of computer hardware or virtual machine that coordinates multiple processors. A Parallel Sysplex relies on one or more Coupling Facilities (CFs). A coupling facility is a mainframe processor (runs in an own LPAR, with dedicated physical CP, defined through Hardware Management Console (HMC)), with memory and special channels (CF Links), and a specialized operating system called Coupling Facility Control Code (CFCC). It has no I/O devices, other than the CF links. The information in the CF resides entirely in memory as CFCC is not a virtual memory operating system. A CF typically has a large memory – of the order of several tens of gigabytes. The CF runs no application software. When originally introduced, the CFCC executed in a separate 9674 mainframe unit that was essentially a processor without I/O facilities other than the CF links. Later IBM enabled the use of an Internal Coupling ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ZIIP
In IBM System z9 and successor mainframes, the System z Integrated Information Processor (zIIP) is a special purpose processor. It was initially introduced to relieve the general mainframe central processors (CPs) of specific Db2 processing loads, but currently is used to offload other z/OS workloads as described below. The idea originated with previous special purpose processors, the zAAP, which offloads Java processing, and the IFL, which runs Linux and z/VM but not other IBM operating systems such as z/OS, DOS/VSE and TPF. A System z PU (processor unit) is "characterized" as one of these processor types, or as a CP (Central Processor), or SAP (System Assist Processor). These processors do not contain microcode or hardware features that accelerate their designated workloads. Instead, by relieving the general CP of particular workloads, they often lead to a higher workload throughput at reduced license fees. DB2 for z/OS V8 was the first application to exploit the zIIP, but no ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Integrated Facility For Linux
The Integrated Facility for Linux (IFL) is an IBM mainframe and Power Systems processor dedicated to running the Linux operating system. On IBM Z and IBM LinuxONE machines, IFLs can be used with or without hypervisors such as z/VM and KVM. IFLs are one of three most common types of "specialty" IBM mainframe processors that give software vendors (and their customers) more granular control over software licensing and maintenance costs. (The other most common specialty processors are and ICFs). Microcode restricts IFLs to Linux workload by omitting some processor instructions not used by the Linux kernel (that other operating systems use), but the underlying processors are physically identical to general purpose processors (CPs). When IBM adds features and performance improvements to its mainframes' general purpose main processors (which can also run Linux), those features and improvements nearly always apply equally to IFLs. In fact, in recent IBM Z machines IFLs support simulta ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Redundant Array Of Independent Memory
A redundant array of independent memory (RAIM) is a design feature found in certain computers' main random access memory. RAIM utilizes additional memory modules and striping algorithms to protect against the failure of any particular module and keep the memory system operating continuously. RAIM is similar in concept to a redundant array of independent disks (RAID), which protects against the failure of a disk drive, but in the case of memory it supports several DRAM device chipkills and entire memory channel failures. RAIM is much more robust than parity checking and ECC memory technologies which cannot protect against many varieties of memory failures. On July 22, 2010, IBM introduced the first high end computer server featuring RAIM, the zEnterprise 196. Each z196 machine contains up to 3 TB (usable) of RAIM-protected main memory. In 2011 the business class model z114 was introduced also supporting RAIM. The formal announcement letter offered some additional information ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
IBM Z14 (microprocessor)
The z14 is a microprocessor made by IBM for their z14 mainframe computers, announced on July 17, 2017. Manufactured at GlobalFoundries' East Fishkill, New York fabrication plant. IBM stated that it is the world's fastest microprocessor by clock rate at 5.2 GHz, with a 10% increased performance per core and 30% for the whole chip compared to its predecessor the z13. Description The Processor Unit chip (PU chip) has an area of 696 mm2 (25.3 × 27.5 mm) and consists of 6.1 billion transistors. It is fabricated using GlobalFoundries' 14 nm FinFET silicon on insulator fabrication process, using 17 layers of metal and supporting speeds of 5.2 GHz, which is higher than its predecessor, the z13. The PU chip has 10 cores but can have 7–10 cores (or "processor units" in IBM's parlance) enabled depending on configuration. The z14 cores support two-way simultaneous multithreading for more applications than previously available. The PU chip is packaged in a s ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
IBM Z15 (microprocessor)
The z15 is a microprocessor made by IBM for their z15 mainframe computers, announced on September 12, 2019. Description The Processor Unit chip (PU chip) has 12 cores. The z15 cores support two-way simultaneous multithreading. The cores implement the CISC z/Architecture with a superscalar, out-of-order pipeline. New in z15 is an on-chip Nest Accelerator Unit, shared by all cores, to accelerate compression Compression may refer to: Physical science *Compression (physics), size reduction due to forces *Compression member, a structural element such as a column *Compressibility, susceptibility to compression * Gas compression *Compression ratio, of a .... The cache (e.g. level 3) is doubled from the previous generation z14, while the "L4 Cache increased from 672MB to 960MB, or +43%" with the new add-on chip System Controller (SC) SCM. Both it and all levels of cache in the main processor from level 1 use eDRAM, instead of the traditionally used SRAM. "A five-CPC drawe ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Neural Net
Artificial neural networks (ANNs), usually simply called neural networks (NNs) or neural nets, are computing systems inspired by the biological neural networks that constitute animal brains. An ANN is based on a collection of connected units or nodes called artificial neurons, which loosely model the neurons in a biological brain. Each connection, like the synapses in a biological brain, can transmit a signal to other neurons. An artificial neuron receives signals then processes them and can signal neurons connected to it. The "signal" at a connection is a real number, and the output of each neuron is computed by some non-linear function of the sum of its inputs. The connections are called ''edges''. Neurons and edges typically have a ''weight'' that adjusts as learning proceeds. The weight increases or decreases the strength of the signal at a connection. Neurons may have a threshold such that a signal is sent only if the aggregate signal crosses that threshold. Typically, n ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
IBM Telum (microprocessor)
The Telum is a microprocessor made by IBM for their IBM Z mainframe computers, announced at the Hot Chips 2021 conference on August 23, 2021. Telum is IBM's first processor that contains on-chip acceleration for AI inferencing while a transaction is taking place. The first Telum-based system was the IBM z16, introduced in April 2022. Description The chip contains 8 processor cores with a deep superscalar out-of-order pipeline, running with more than 5 GHz clock frequency, optimized for the demands of heterogenous enterprise class workloads. The completely redesigned cache and chip-interconnection infrastructure provides 32 MB cache per core, and can scale to 32 Telum chips. The dual-chip module design contains 22 billion transistors and 19 miles of wire on 17 metal layers. See also * z/Architecture * IBM System z IBM Z is a family name used by IBM for all of its z/Architecture mainframe computers. In July 2017, with another generation of products, the official fa ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
