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Comparison Of CPU Microarchitectures
The following is a comparison of CPU microarchitectures. See also * Processor design * Comparison of instruction set architectures An instruction set architecture (ISA) is an abstract model of a computer, also referred to as computer architecture. A realization of an ISA is called an ''implementation''. An ISA permits multiple implementations that may vary in performance, phys ... References {{Processor technologies Computer architecture Computing comparisons ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Central Processing Unit
A central processing unit (CPU), also called a central processor, main processor or just processor, is the electronic circuitry that executes instructions comprising a computer program. The CPU performs basic arithmetic, logic, controlling, and input/output (I/O) operations specified by the instructions in the program. This contrasts with external components such as main memory and I/O circuitry, and specialized processors such as graphics processing units (GPUs). The form, design, and implementation of CPUs have changed over time, but their fundamental operation remains almost unchanged. Principal components of a CPU include the arithmetic–logic unit (ALU) that performs arithmetic and logic operations, processor registers that supply operands to the ALU and store the results of ALU operations, and a control unit that orchestrates the fetching (from memory), decoding and execution (of instructions) by directing the coordinated operations of the ALU, registers and oth ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
Byte
The byte is a unit of digital information that most commonly consists of eight bits. Historically, the byte was the number of bits used to encode a single character of text in a computer and for this reason it is the smallest addressable unit of memory in many computer architectures. To disambiguate arbitrarily sized bytes from the common 8-bit definition, network protocol documents such as The Internet Protocol () refer to an 8-bit byte as an octet. Those bits in an octet are usually counted with numbering from 0 to 7 or 7 to 0 depending on the bit endianness. The first bit is number 0, making the eighth bit number 7. The size of the byte has historically been hardware-dependent and no definitive standards existed that mandated the size. Sizes from 1 to 48 bits have been used. The six-bit character code was an often-used implementation in early encoding systems, and computers using six-bit and nine-bit bytes were common in the 1960s. These systems often had memory wo ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM Cortex-A53
The ARM Cortex-A53 is one of the first two central processing units implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Cambridge design centre. The Cortex-A53 is a 2-wide decode superscalar processor, capable of dual-issuing some instructions. It was announced October 30, 2012 and is marketed by ARM as either a stand-alone, more energy-efficient alternative to the more powerful Cortex-A57 microarchitecture, or to be used alongside a more powerful microarchitecture in a big.LITTLE configuration. It is available as an IP core to licensees, like other ARM intellectual property and processor designs. Overview * 8-stage pipelined processor with 2-way superscalar, in-order execution pipeline * DSP and NEON SIMD extensions are mandatory per core * VFPv4 Floating Point Unit onboard (per core) * Hardware virtualization support * TrustZone security extensions * 64-byte cache lines * 10-entry L1 TLB, and 512-entry L2 TLB * 4KiB conditional branch predictor, 25 ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM Cortex-A15 MPCore
The ARM Cortex-A15 MPCore is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. It is a multicore processor with out-of-order superscalar pipeline running at up to 2.5 GHz. Overview ARM has claimed that the Cortex-A15 core is 40 percent more powerful than the Cortex-A9 core with the same number of cores at the same speed. The first A15 designs came out in the autumn of 2011, but products based on the chip did not reach the market until 2012. Key features of the Cortex-A15 core are: * 40-bit Large Physical Address Extensions (LPAE) addressing up to 1 TB of RAM. As per the x86 Physical Address Extension, virtual address space remains 32 bit. * 15 stage integer/17–25 stage floating point pipeline, with out-of-order speculative issue 3-way superscalar execution pipeline * 4 cores per cluster, up to 2 clusters per chip with CoreLink 400 (CCI-400, an AMBA-4 coherent interconnect) and 4 clusters per chip with CCN-504. ARM provid ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM Cortex-A9 MPCore
The ARM Cortex-A9 MPCore is a 32-bit multi-core processor that provides up to 4 cache-coherent cores, each implementing the ARM v7 architecture instruction set. It was introduced in 2007. Features Key features of the Cortex-A9 core are: * Out-of-order speculative issue superscalar execution 8-stage pipeline giving 2.50 DMIPS/MHz/core. * NEON SIMD instruction set extension performing up to 16 operations per instruction (optional). * High performance VFPv3 floating point unit doubling the performance of previous ARM FPUs (optional). * Thumb-2 instruction set encoding reduces the size of programs with little impact on performance. * TrustZone security extensions. * Jazelle DBX support for Java execution. * Jazelle RCT for JIT compilation. * Program Trace Macrocell and CoreSight Design Kit for non-intrusive tracing of instruction execution. * L2 cache controller (0–4 MB). * Multi-core processing. ARM states that the TSMC 40G hard macro implementation typically ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM Cortex-A8
The ARM Cortex-A8 is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture. Compared to the ARM11, the Cortex-A8 is a dual-issue superscalar design, achieving roughly twice the instructions per cycle. The Cortex-A8 was the first Cortex design to be adopted on a large scale in consumer devices. Features Key features of the Cortex-A8 core are: * Frequency from 600 MHz to 1 GHz and above * Superscalar dual-issue microarchitecture * NEON SIMD instruction set extension * 13-stage integer pipeline and 10-stage NEON pipeline * VFPv3 Floating Point Unit * Thumb-2 instruction set encoding * Jazelle RCT (Also known as ThumbEE instruction set) * Advanced branch prediction unit with >95% accuracy * Integrated level 2 Cache (0–4 MiB) * 2.0 DMIPS/MHz Chips Several system-on-chips (SoC) have implemented the Cortex-A8 core, including: * Allwinner A1X * Apple A4 * Freescale Semiconductor i.MX51 * Rockchip RK2918, RK2906 * Samsung ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM Cortex-A7 MPCore
The ARM Cortex-A7 MPCore is a 32-bit microprocessor core licensed by ARM Holdings implementing the ARMv7-A architecture announced in 2011. Overview It has two target applications; firstly as a smaller, simpler, and more power-efficient successor to the Cortex-A8. The other use is in the big.LITTLE architecture, combining one or more A7 cores with one or more Cortex-A15 cores into a heterogeneous system. To do this it is fully feature-compatible with the A15. Key features of the Cortex-A7 core are: * Partial dual-issue, in-order microarchitecture with an 8-stage pipeline * NEON SIMD instruction set extension * VFPv4 Floating Point Unit * Thumb-2 instruction set encoding * Jazelle RCT * Hardware virtualization * Large Page Address Extensions (LPAE) * Integrated level 2 Cache (0–1 MB) * 1.9 DMIPS / MHz * Typical clock speed 1.5 GHz Chips Several system-on-chips (SoC) have implemented the Cortex-A7 core, including: * Allwinner A20 (dual-core A7 + Mali-400 MP2 GP ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM Cortex-A5
The ARM Cortex-A5 is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture announced in 2009. Overview The Cortex-A5 is intended to replace the ARM9 and ARM11 cores for use in low-end devices. The Cortex-A5 offers features of the ARMv7 architecture focusing on internet applications e.g. VFPv4 and NEON advanced SIMD. Key features of the Cortex-A5 core are: * Single-issue, in-order microarchitecture with an 8-stage pipeline * NEON SIMD instruction set extension (optional) * VFPv4 floating-point unit (optional) * Thumb-2 instruction set encoding * Jazelle RCT * 1.57 DMIPS / MHz Chips Several system-on-chips (SoC) have implemented the Cortex-A5 core, including: * Actions Semiconductor ATM7029 (gs702a) is a quad-core Cortex-A5 configuration * AMD Fusion APUs include a Cortex-A5 as a security co-processor * Amlogic S805, M805 and A111 * Analog Devices ADSP-SC57x, ADSP-SC58x series ARM Cortex-A5 + SHARC+ multicore DSP * Atmel SAMA5Dxx * Free ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM11
ARM11 is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings. The ARM11 core family consists of ARM1136J(F)-S, ARM1156T2(F)-S, ARM1176JZ(F)-S, and ARM11MPCore. Since ARM11 cores were released from 2002 to 2005, they are no longer recommended for new IC designs, instead ARM Cortex-A and ARM Cortex-R cores are preferred. Overview The ARM11 microarchitecture (announced 29 April 2002) introduced the ARMv6 architectural additions which had been announced in October 2001. These include SIMD media instructions, multiprocessor support and a new cache architecture. The implementation included a significantly improved instruction processing pipeline, compared to previous ARM9 or ARM10 families, and is used in smartphones from Apple, Nokia, and others. The initial ARM11 core (ARM1136) was released to licensees in October 2002. The ARM11 family are currently the only ARMv6-architecture cores. There are, however, ARMv6-M cores ( Cortex-M0 and Cortex-M1), addressing ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
XScale
XScale is a microarchitecture for central processing units initially designed by Intel implementing the ARM architecture (version 5) instruction set. XScale comprises several distinct families: IXP, IXC, IOP, PXA and CE (see more below), with some later models designed as system-on-a-chip (SoC). Intel sold the PXA family to Marvell Technology Group in June 2006. Marvell then extended the brand to include processors with other microarchitectures, like ARM's Cortex. The XScale architecture is based on the ARMv5TE ISA without the floating-point instructions. XScale uses a seven-stage integer and an eight-stage memory super- pipelined microarchitecture. It is the successor to the Intel StrongARM line of microprocessors and microcontrollers, which Intel acquired from DEC's Digital Semiconductor division as part of a settlement of a lawsuit between the two companies. Intel used the StrongARM to replace its ailing line of outdated RISC processors, the i860 and i960. All the generation ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM9
ARM9 is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use. The ARM9 core family consists of ARM9TDMI, ARM940T, ARM9E-S, ARM966E-S, ARM920T, ARM922T, ARM946E-S, ARM9EJ-S, ARM926EJ-S, ARM968E-S, ARM996HS. Since ARM9 cores were released from 1998 to 2006, they are no longer recommended for new IC designs, instead ARM Cortex-A, ARM Cortex-M, ARM Cortex-R cores are preferred. Overview With this design generation, ARM moved from a von Neumann architecture (Princeton architecture) to a (modified; meaning split cache) Harvard architecture with separate instruction and data buses (and caches), significantly increasing its potential speed. Most silicon chips integrating these cores will package them as modified Harvard architecture chips, combining the two address buses on the other side of separated CPU caches and tightly coupled memories. There are two subfamilies, implementing different ARM architecture versions. Differences ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
ARM7
ARM7 is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings for microcontroller use. The ARM7 core family consists of ARM700, ARM710, ARM7DI, ARM710a, ARM720T, ARM740T, ARM710T, ARM7TDMI, ARM7TDMI-S, ARM7EJ-S. The ARM7TDMI and ARM7TDMI-S were the most popular cores of the family. Since ARM7 cores were released from 1993 to 2001, they are no longer recommended for new IC designs; instead ARM Cortex-M or ARM Cortex-R cores are preferred. Overview This generation introduced the Thumb 16-bit instruction set providing improved code density compared to previous designs. The most widely used ARM7 designs implement the ARMv4T architecture, but some implement ARMv3 or ARMv5TEJ. ARM7TDMI has 37 registers (31 GPR and 6 SPR). All these designs use a Von Neumann architecture, thus the few versions containing a cache do not separate data and instruction caches. Some ARM7 cores are obsolete. One historically significant model, the ARM7DI"ARM7DI Data Sheet"; Docu ... [...More Info...] [...Related Items...] OR: [Wikipedia] [Google] [Baidu] |
